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DUAL DEPLETIN CMOS (D2CMOS) STATIC MEMORY CELL.

Author
TAKAGI H; KANO G
MATSUSHITA ELECTRONICS CORP., TAKATSUKI, OSAKA, JAP.
Source
I.E.E.E.J. SOLID-STATE CIRCUITS; U.S.A.; DA. 1977; VOL. 12; NO 4; PP. 424-426; BIBL. 8 REF.
Document type
Article
Language
English
Keyword (fr)
MEMOIRE STRUCTURE MOS MEMOIRE STATIQUE TECHNOLOGIE MOS COMPLEMENTAIRE MODE APPAUVRISSEMENT FABRICATION MICROELECTRONIQUE TECHNOLOGIE SUBSTRAT SILICIUM SUR SAPHIR APPAUVRISSEMENT DOUBLE ELECTRONIQUE
Keyword (en)
MEMORY MOS STRUCTURE STATIC STORAGE COMPLEMENTARY MOS TECHNOLOGY DEPLETION MODE MICROELECTRONIC FABRICATION TECHNOLOGY SILICON ON SAPPHIRE SUBSTRATE ELECTRONICS
Keyword (es)
ELECTRONICA
Classification
Pascal
001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics

Discipline
Electronics
Origin
Inist-CNRS
Database
PASCAL
INIST identifier
PASCAL7830130813

Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS

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