AN INTEGRATED TEST CONCEPT FOR SWITCHED-CAPACITOR DYNAMIC MOS RAM'S.
- Author
- LO TC; GUIDRY MR
FAIRCHILD CAMERA AND INSTRUMENT, MOUNTAIN VIEW, CALIF. 94040 - Source
- I.E.E.E. J. SOLID-STATE CIRCUITS; U.S.A.; DA. 1977; VOL. 12; NO 6; PP. 693-703; BIBL. 11 REF.
- Document type
- Article
- Language
- English
- Keyword (fr)
- ESSAI MEMOIRE CAPACITE ELECTRIQUE COMMUTATION STRUCTURE MOS MEMOIRE VIVE MEMOIRE DYNAMIQUE ELECTRONIQUE
- Keyword (en)
- TEST MEMORY CAPACITANCE SWITCHING MOS STRUCTURE DYNAMICAL STORAGE ELECTRONICS
- Keyword (es)
- ELECTRONICA
- Classification
- Discipline
- Electronics
- Origin
- Inist-CNRS
- Database
- PASCAL
- INIST identifier
- PASCAL7830466261
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
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