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EXCESS GATE CURRENT ANALYSIS OF JUNCTION GATE FET'S BY TWO-DIMENSIONAL COMPUTER SIMULATION

Author
YAMAGUCHI K; ASAI S
HITACHI LTD, TOKYO, JPN
Source
I.E.E.E. TRANS. ELECTRON. DEVICES; USA; DA. 1978; VOL. 25; NO 3; PP. 362-369; BIBL. 12 REF.
Document type
Article
Language
English
Keyword (fr)
TRANSISTOR EFFET CHAMP JONCTION COURANT ELECTRIQUE IONISATION CHOC TENSION AVALANCHE ANALYSE ASSISTEE ORDINATEUR TRANSISTOR EFFET CHAMP SIMULATION NUMERIQUE ANALYSE BIDIMENSIONNELLE ELECTRONIQUE
Keyword (en)
JUNCTION FIELD EFFECT TRANSISTOR ELECTRICAL CURRENTS IMPACT IONIZATION AVALANCHE VOLTAGE FIELD EFFECT TRANSISTOR DIGITAL SIMULATION TWO DIMENSIONAL ANALYSIS ELECTRONICS
Keyword (es)
ELECTRONICA
Classification
Pascal
001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics

Discipline
Electronics
Origin
Inist-CNRS
Database
PASCAL
INIST identifier
PASCAL7930188811

Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS

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