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AL COVERAGE OF SURFACE STEPS AT SIO2 INSULATED POLYCRISTALLINE SI BOUNDARIES: AL EVAPORATION IN VACUUM AND LOW PRESSURE AR

Author
SILVESTRI VJ; RIDEOUT VL; MANISCALCO V
IBM THOMAS J. WATSON RES. CENT.,YORKTOWN HEIGHTS NY 10598,USA
Source
J. ELECTROCHEM. SOC.; ISSN 0013-4651; USA; DA. 1979; VOL. 126; NO 8; PP. 1335-1338; BIBL. 10 REF.
Document type
Article
Language
English
Keyword (fr)
FABRICATION MICROELECTRONIQUE INTERCONNEXION VIDE FORMATION ALUMINIUM SILICIUM POLYCRISTAL TRANSISTOR EFFET CHAMP DEPOT CHIMIQUE PHASE VAPEUR CIRCUIT INTEGRE FIABILITE ELECTRONIQUE
Keyword (en)
MICROELECTRONIC FABRICATION INTERCONNECTION VACUUM ALUMINUM SILICON POLYCRYSTAL FIELD EFFECT TRANSISTOR CHEMICAL VAPOR DEPOSITION INTEGRATED CIRCUIT RELIABILITY ELECTRONICS
Keyword (es)
ELECTRONICA
Classification
Pascal
001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics

Discipline
Electronics
Origin
Inist-CNRS
Database
PASCAL
INIST identifier
PASCAL8030115418

Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS

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