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A TESTABLE DESIGN OF ITERATIVE LOGIC ARRAYS

Author
PARTHASARATHY R; REDDY SM
UNIV. IOWA, DEP. ELECTR. COMPUTER ENG./IOWA CITY IA 52242/USA
Source
IEEE TRANS. CIRCUITS SYST.; ISSN 0098-4094; USA; DA. 1981; VOL. 28; NO 11; PP. 1037-1045; BIBL. 11 REF.
Document type
Article
Language
English
Keyword (fr)
CONCEPTION CIRCUIT RESEAU LOGIQUE DETECTION PANNE FIABILITE CIRCUIT LSI CIRCUIT LOGIQUE ESSAI C ESSAI UNE ETAPE RESEAU LOGIQUE ITERATIF ELECTRONIQUE
Keyword (en)
RELIABILITY ELECTRONICS
Keyword (es)
ELECTRONICA
Classification
Pascal
001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics

Discipline
Electronics
Origin
Inist-CNRS
Database
PASCAL
INIST identifier
PASCAL82X0124890

Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS

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