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Hardwired MPEG-4 repetitive paddingKUZMANOV, Georgi; VASSILIADIS, Stamatis; VAN EIJNDHOVEN, Jos T. J et al.IEEE transactions on multimedia. 2005, Vol 7, Num 2, pp 261-268, issn 1520-9210, 8 p.Article
Efficient techniques and hardware analysis for mesh-connected processorsWU JIGANG; SRIKANTHAN, Thambipillai; HEIKO, Schröder et al.Lecture notes in computer science. 2005, pp 442-446, issn 0302-9743, isbn 3-540-29235-7, 1Vol, 5 p.Conference Paper
Technology of Express5800/ft serverMISAKA, Toshio; KANEKO, Akihiro.NEC research & development. 2002, Vol 43, Num 2, pp 166-170, issn 0547-051XArticle
Serial-parallel tradeoff analysis of all-pairs shortest path algorithms in reconfigurable computingMAK, Sui-Tung; LAM, Kai-Pui.IEEE international conference on field-programmable technology. 2002, pp 302-305, isbn 0-7803-7574-2, 4 p.Conference Paper
Experiments with sequential prefetchingMANOHARAN, Sathiamoorthy; CHAITANYA REDDY YAVASANI.Lecture notes in computer science. 2001, pp 322-331, issn 0302-9743, isbn 3-540-42293-5Conference Paper
Code positioning for VLIW architecturesCILIO, Andrea G. M; CORPORAAL, Henk.Lecture notes in computer science. 2001, pp 332-343, issn 0302-9743, isbn 3-540-42293-5Conference Paper
Reordering memory bus transactions for reduced power consumptionCHILDERS, Bruce R; NAKRA, Tarun.Lecture notes in computer science. 2001, pp 146-161, issn 0302-9743, isbn 3-540-41781-8Conference Paper
Java consistency : Nonoperational characterizations for Java memory behaviorGONTMAKHER, Alex; SCHUSTER, Assaf.ACM transactions on computer systems. 2000, Vol 18, Num 4, pp 333-386, issn 0734-2071Article
Cost-efficient branch target buffersHOOGERBRUGGE, J.Lecture notes in computer science. 2000, pp 950-959, issn 0302-9743, isbn 3-540-67956-1Conference Paper
A specific test methodology for symmetric SRAM-based FPGAsRENOVELL, M.Lecture notes in computer science. 2000, pp 300-311, issn 0302-9743, isbn 3-540-67899-9Conference Paper
A new floorplanning method for FPGA architectural researchWOLZ, F; KOLLA, R.Lecture notes in computer science. 2000, pp 432-442, issn 0302-9743, isbn 3-540-67899-9Conference Paper
A self-reconfigurable gate array architectureSIDHU, R; WADHWA, S; MEI, A et al.Lecture notes in computer science. 2000, pp 106-120, issn 0302-9743, isbn 3-540-67899-9Conference Paper
A new home-based software DSM protocol for SMP clustersWEIWU HU; FUXIN ZHANG; HAIMING LIU et al.Lecture notes in computer science. 2000, pp 1132-1142, issn 0302-9743, isbn 3-540-67956-1Conference Paper
FPL 2000 : field-programmable logic and applications : the roadmap to reconfigurable computing (Villach, 27-30 August 2000)Hartenstein, Reiner W; Grünbacher, Herbert.Lecture notes in computer science. 2000, issn 0302-9743, isbn 3-540-67899-9, XVII, 856 p, isbn 3-540-67899-9Conference Proceedings
A hardware architecture for scheduling complex real-time task setsSAEZ, Sergio; VILA, Joan; CRESPO, Alfons et al.CIT. Journal of computing and information technology. 2000, Vol 8, Num 3, pp 235-247, issn 1330-1136Article
An analytic model for communication latency in wormhole-switched k-ary n-cube interconnection networks with digit-reversal trafficSARBAZI-AZAD, H; MACKENZIE, L. M; OULD-KHAOUA, M et al.Lecture notes in computer science. 2000, pp 218-229, issn 0302-9743, isbn 3-540-41128-3Conference Paper
Hardware modeling using function encapsulationSAWADA, Jun; HUNT, Warren A.Lecture notes in computer science. 2000, pp 234-245, issn 0302-9743, isbn 3-540-41219-0Conference Paper
Symbiotic jobscheduling for a simultaneous multithreading processorSNAVELY, Allan; TULLSEN, Dean M.Operating systems review. 2000, Vol 34, Num 5, pp 234-244, issn 0163-5980Conference Paper
Quantifying loop nest locality using SPEC'95 and the Perfect BenchmarksMCKINLEY, K. S; TEMAM, O.ACM transactions on computer systems. 1999, Vol 17, Num 4, pp 288-336, issn 0734-2071Article
Comprehensive hardware and software support for operating systems to exploit MP memory hierarchiesCHUN XIA; TORRELLAS, J.IEEE transactions on computers. 1999, Vol 48, Num 5, pp 494-505, issn 0018-9340Article
Temporal partitioning and scheduling data flow graphs for reconfigurable computers : Special section on configurable computingGAJJALA PURNA, K. M; BHATIA, D.IEEE transactions on computers. 1999, Vol 48, Num 6, pp 579-590, issn 0018-9340Article
An introduction to OCEANS projectWIJSHOFF, H. A. G.Lecture notes in computer science. 1999, pp 5-6, issn 0302-9743, isbn 3-540-65969-2Conference Paper
M Parallel DB/DC for a large-scale and flexible information systemYAMANE, T; MATSUSHITA, K; KATOU, K et al.Hitachi review. 1996, Vol 45, Num 5, pp 243-248, issn 0018-277XArticle
Strategic directions in computer architectureMUDGE, T; ARVIND; SMITH, J et al.ACM computing surveys. 1996, Vol 28, Num 4, pp 671-678, issn 0360-0300Conference Paper
A new scheme for cache coherence in multiprocessor systemsCHAUDHRY, G. M; HAN, W.International journal of modelling & simulation. 1995, Vol 15, Num 4, pp 148-153, issn 0228-6203Article