Factoring logic functionsBRAYTON, R. K.IBM journal of research and development. 1987, Vol 31, Num 2, pp 187-198, issn 0018-8646Article

Heuristic minimization of multiple-valued relationsWATANABE, Y; BRAYTON, R. K.IEEE transactions on computer-aided design of integrated circuits and systems. 1993, Vol 12, Num 10, pp 1458-1472, issn 0278-0070Article

Performance planningOTTEN, R. H. J. M; BRAYTON, R. K.Integration (Amsterdam). 2000, Vol 29, Num 1, pp 1-24, issn 0167-9260Article

Permissible functions for multioutput components in combinational logic optimizationWATANABE, Y; GUERRA, L. M; BRAYTON, R. K et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1996, Vol 15, Num 7, pp 732-744, issn 0278-0070Article

Testing language containment for ω-automata using BDDsTOUATI, H. J; BRAYTON, R. K; KURSHAN, R et al.Information and computation (Print). 1995, Vol 118, Num 1, pp 101-109, issn 0890-5401Article

STARI : A case study in compositional and hierarchical timing verificationTASIRAN, S; BRAYTON, R. K.Lecture notes in computer science. 1997, pp 191-201, issn 0302-9743, isbn 3-540-63166-6Conference Paper

Computing the initial states of retimed circuitsTOUATI, H. J; BRAYTON, R. K.IEEE transactions on computer-aided design of integrated circuits and systems. 1993, Vol 12, Num 1, pp 157-162, issn 0278-0070Article

Correction to Optimal state assignment for finite state machinesDE MICHELI, G; BRAYTON, R. K; SANGIOVANNI-VINCENTELLI, A et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1986, Vol 5, Num 1, issn 0278-0070, 239Article

Logic operations are properties of computer-simulated interactions between excitable dendritic spinesSHEPHERD, G. M; BRAYTON, R. K.Neuroscience. 1987, Vol 21, Num 1, pp 151-165, issn 0306-4522Article

Optimal state assignment for finite state machinesDE MICHELI, G; BRAYTON, R. K; SANGIOVANNI-VINCENTELLI, A et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1985, Vol 4, Num 3, pp 269-285, issn 0278-0070Article

Integration of retiming with architectural floorplanningTABBARA, A; TABBARA, B; BRAYTON, R. K et al.Integration (Amsterdam). 2000, Vol 29, Num 1, pp 25-43, issn 0167-9260Article

Symbolic minimization of multilevel logic and the input encoding problemMALIK, S; LAVAGNO, L; BRAYTON, R. K et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1992, Vol 11, Num 7, pp 825-843, issn 0278-0070Article

Multilevel logic synthesisBRAYTON, R. K; HACHTEL, G. D; SANGIOVANNI-VINCENTELLI, A. L et al.Proceedings of the IEEE. 1990, Vol 78, Num 2, pp 264-300, issn 0018-9219, 37 p.Article

Combinational test generation using satisfiabilitySTEPHAN, P; BRAYTON, R. K; SANGIOVANNI-VINCENTELLI, A. L et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1996, Vol 15, Num 9, pp 1167-1176, issn 0278-0070Article

Circuit structure relations to redundancy and delaySALDANHA, A; BRAYTON, R. K; SANGIOVANNI-VINCENTELLI, A. L et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1994, Vol 13, Num 7, pp 875-883, issn 0278-0070Article

Symbolic two-level minimizationVILLA, T; SALDANHA, A; BRAYTON, R. K et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1997, Vol 16, Num 7, pp 692-708, issn 0278-0070Article

Delay fault coverage, test set size, and performance trade-offsLAM, W. K; SALDANHA, A; BRAYTON, R. K et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1995, Vol 14, Num 1, pp 32-44, issn 0278-0070Article

Performance optimization of pipelined logic circuits using peripheral retiming and resynthesisSHARAD MALIK; KANWAR JIT SINGH; BRAYTON, R. K et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1993, Vol 12, Num 5, pp 568-578, issn 0278-0070Article

Two-level minimization of multivalued functions with large offsetsMALIK, A. A; BRAYTON, R. K; NEWTON, A. R et al.IEEE transactions on computers. 1993, Vol 42, Num 11, pp 1325-1342, issn 0018-9340Article

A timed automaton-based method for accurate computation of circuit delay in the presence of cross-talkTASIRAN, S; KHATRI, S. P; YOVINE, S et al.Lecture notes in computer science. 1998, pp 149-166, issn 0302-9743, isbn 3-540-65191-8Conference Paper

Implicit computation of compatible sets for state minimization of ISFSM'sKAM, T; VILLA, T; BRAYTON, R. K et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1997, Vol 16, Num 7, pp 657-676, issn 0278-0070Article

Computing reachable control states of systems modeled with uninterpreted functions and infinite memoryISLES, A. J; HOJATI, R; BRAYTON, R. K et al.Lecture notes in computer science. 1998, pp 256-267, issn 0302-9743, isbn 3-540-64608-6Conference Paper

Valid clock frequencies and their computation in wavepipelined circuitsLAM, W. K. C; BRAYTON, R. K; SANGIOVANNI-VINCENTELLI, A. L et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1996, Vol 15, Num 7, pp 791-807, issn 0278-0070Article

Signal enhancement in distal cortical dendrites by means of interactions between active dendritic spinesSHEPHERD, G. M; BRAYTON, R. K; MILLER, J. P et al.Proceedings of the National Academy of Sciences of the United States of America. 1985, Vol 82, Num 7, pp 2192-2195, issn 0027-8424Article

Theory and algorithms for face hypercube embeddingGOLDBERG, E. I; VILLA, T; BRAYTON, R. K et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1998, Vol 17, Num 6, pp 472-488, issn 0278-0070Article