A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN SearchingAN, Fengwei; KOIDE, Tetsushi; MATTAUSCH, Hans Jürgen et al.IEICE transactions on information and systems. 2012, Vol 95, Num 9, pp 2327-2338, issn 0916-8532, 12 p.Article

4-Port unified data/instruction cache design with distributed crossbar and interleaved cache-line wordsJOHGUCHI, Koh; MATTAUSCH, Hans Jürgen; KOIDE, Tetsushi et al.IEICE transactions on electronics. 2007, Vol 90, Num 11, pp 2157-2160, issn 0916-8524, 4 p.Article

Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage SystemsKUMAKI, Takeshi; KOIDE, Tetsushi; MATTAUSCH, Hans Jürgen et al.IEICE transactions on information and systems. 2011, Vol 94, Num 9, pp 1742-1754, issn 0916-8532, 13 p.Article

Low power bank-based multi-port SRAM design due to bank standby modeZHAOMIN ZHU; JOHGUCHI, Koh; MATTAUSCH, Hans Jürgen et al.MWSCAS : Midwest symposium on circuits and systems. 2004, isbn 0-7803-8346-X, 3Vol, Vol I, 569-572Conference Paper

Analog-circuit-component optimization with genetic algorithmTAKEMURA, Kazuhiro; KOIDE, Tetsushi; MATTAUSCH, Hans Jurgen et al.MWSCAS : Midwest symposium on circuits and systems. 2004, isbn 0-7803-8346-X, 3Vol, Vol I, 489-492Conference Paper

Acceleration of DCT processing with massive-parallel memory-embedded SIMD matrix processorKUMAKI, Takeshi; ISHIZAKI, Masakatsu; KOIDE, Tetsushi et al.IEICE transactions on information and systems. 2007, Vol 90, Num 8, pp 1312-1315, issn 0916-8532, 4 p.Article

Embedded low-power dynamic TCAM architecture with transparently scheduled refresh : Lower-power LSI and lower-power IPNODA, Hideyuki; INOUE, Kazunari; MATTAUSCH, Hans Jürgen et al.IEICE transactions on electronics. 2005, Vol 88, Num 4, pp 622-629, issn 0916-8524, 8 p.Article

On the validity of conventional MOSFET nonlinearity characterization at RF switchingNAVARRO, Dondee; TAKEDA, Youichi; MIURA-MATTAUSCH, Mitiko et al.IEEE microwave and wireless components letters. 2006, Vol 16, Num 3, pp 125-127, issn 1531-1309, 3 p.Article

Compact Modeling of Expansion Effects in LDMOSHZUKA, Takahiro; SAKUDA, Takashi; ORITSUKI, Yasunori et al.IEICE transactions on electronics. 2012, Vol 95, Num 11, pp 1817-1823, issn 0916-8524, 7 p.Article

A carrier-transit-delay-based nonquasi-static MOSFET model for circuit simulation and its application to harmonic distortion analysisNAVARRO, Dondee; TAKEDA, Youichi; MIYAKE, Masataka et al.I.E.E.E. transactions on electron devices. 2006, Vol 53, Num 9, pp 2025-2034, issn 0018-9383, 10 p.Article

Completely surface-potential-based compact model of the fully depleted SOI-MOSFET including short-channel effectsSADACHIKA, Norio; KITAMARU, Daisuke; UETSUJI, Yasuhito et al.I.E.E.E. transactions on electron devices. 2006, Vol 53, Num 9, pp 2017-2024, issn 0018-9383, 8 p.Article

Fully-parallel pattern-matching engine with dynamic adaptability to Hamming or Manhattan distanceMATTAUSCH, Hans Jürgen; OMORI, Nobuhiko; FUKAE, Seiji et al.2002 symposium on VLSI circuits. 2002, pp 252-255, isbn 0-7803-7310-3, 4 p.Conference Paper

Quasi-2-Dimensional Compact Resistor Model for the Drift Region in High-Voltage LDMOS DevicesTANAKA, Akihiro; ORITSUKI, Yasunori; KIKUCHIHARA, Hideyuki et al.I.E.E.E. transactions on electron devices. 2011, Vol 58, Num 7, pp 2072-2080, issn 0018-9383, 9 p.Article

Modeling of NBTI Stress Induced Hole-Trapping and Interface-State-Generation Mechanisms under a Wide Range of Bias ConditionsCHENYUE MA; MATTAUSCH, Hans Jürgen; MIURA-MATTAUSCH, Mitiko et al.IEICE transactions on electronics. 2013, Vol 96, Num 10, pp 1339-1347, issn 0916-8524, 9 p.Article

Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor : Advanced processors based on novel concepts in computationKUMAKI, Takeshi; ISHIZAKI, Masakatsu; KOIDE, Tetsushi et al.IEICE transactions on electronics. 2008, Vol 91, Num 9, pp 1409-1418, issn 0916-8524, 10 p.Article

A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architectureNODA, Hideyuki; INOUE, Kazunari; HAYASHI, Isamu et al.IEEE journal of solid-state circuits. 2005, Vol 40, Num 1, pp 245-253, issn 0018-9200, 9 p.Conference Paper

HiSIM2 : Advanced MOSFET model valid for RF circuit simulationMIURA-MATTAUSCH, Mitiko; SADACHIKA, Norio; MATTAUSCH, Hans Jürgen et al.I.E.E.E. transactions on electron devices. 2006, Vol 53, Num 9, pp 1994-2007, issn 0018-9383, 14 p.Article

1/f-noise characteristics in 100 nm-MOSFETs and its modeling for circuit simulationMATSUMOTO, Shizunori; UENO, Hiroaki; NAKAYAMA, Noriaki et al.IEICE transactions on electronics. 2005, Vol 88, Num 2, pp 247-254, issn 0916-8524, 8 p.Article

A compact model of the pinch-off region of 100 nm MOSFETs based on the surface-potentialNAVARRO, Dondee; MIZOGUCHI, Takeshi; NAKAYAMA, Noriaki et al.IEICE transactions on electronics. 2005, Vol 88, Num 5, pp 1079-1086, issn 0916-8524, 8 p.Article