Compact Modeling of the p-i-n Diode Reverse Recovery Effect Valid for both Low and High Current-Density ConditionsMIYAKE, Masataka; NAKASHIMA, Junichi; MIURA-MATTAUSCH, Mitiko et al.IEICE transactions on electronics. 2012, Vol 95, Num 10, pp 1682-1688, issn 0916-8524, 7 p.Article

The Second-Generation of HiSIM_HV Compact Models for High-Voltage MOSFETs : ADVANCED MODELING OF POWER DEVICES AND THEIR APPLICATIONSJÜRGEN MATTAUSCH, Hans; MIYAKE, Masataka; IIZUKA, Takahiro et al.I.E.E.E. transactions on electron devices. 2013, Vol 60, Num 2, pp 653-661, issn 0018-9383, 9 p.Article

Compact Double-Gate Metal-Oxide-Semiconductor Field Effect Transistor Model for Device/Circuit OptimizationSADACHIKA, Norio; MURAKAMI, Takahiro; OKA, Hideki et al.IEICE transactions on electronics. 2008, Vol 91, Num 8, pp 1379-1381, issn 0916-8524, 3 p.Article

Shot noise modeling in metal-oxide-semiconductor field effect transistors under sub-threshold conditionISOBE, Yoshioki; HARA, Kiyohito; NAVARRO, Dondee et al.IEICE transactions on electronics. 2007, Vol 90, Num 4, pp 885-894, issn 0916-8524, 10 p.Article

Degradation of 4H-SiC IGBT threshold characteristics due to SiC/SiO₂ interface defectsPESIC, Iliya; NAVARRO, Dondee; MIYAKE, Masataka et al.Solid-state electronics. 2014, Vol 101, pp 126-130, issn 0038-1101, 5 p.Conference Paper

A Gate-Current Model for Advanced MOSFET Technologies Implemented into HiSIM2INAGAKI, Ryosuke; SADACHIKA, Norio; NAVARRO, Dondee et al.IEEJ transactions on electrical and electronic engineering. 2008, Vol 3, Num 1, pp 64-71, issn 1931-4973, 8 p.Article

Prediction of Circuit-Performance Variations from Technology Variations for Reliable 100 nm SOC Circuit DesignSADACHIKA, Norio; MIMURA, Shu; YUMISAKI, Akihiro et al.IEICE transactions on electronics. 2011, Vol 94, Num 3, pp 361-367, issn 0916-8524, 7 p.Article

Modeling of the Impurity-Gradient Effect in High-Voltage Laterally Diffused MOSFETs : ADVANCED MODELING OF POWER DEVICES AND THEIR APPLICATIONSIIZUKA, Takahiro; FUKUSHIMA, Kenji; TANAKA, Akihiro et al.I.E.E.E. transactions on electron devices. 2013, Vol 60, Num 2, pp 684-690, issn 0018-9383, 7 p.Article

Correlating Microscopic and Macroscopic Variation With Surface-Potential Compact ModelMATTAUSCH, Hans J; SADACHIKA, Norio; YUMISAKI, Akihiro et al.IEEE electron device letters. 2009, Vol 30, Num 8, pp 873-875, issn 0741-3106, 3 p.Article

Modeling of Trench-Gate Type HV-MOSFETs for Circuit SimulationIIZUKA, Takahiro; FUKUSHIMA, Kenji; TANAKA, Akihiro et al.IEICE transactions on electronics. 2013, Vol 96, Num 5, pp 744-751, issn 0916-8524, 8 p.Article

On the validity of conventional MOSFET nonlinearity characterization at RF switchingNAVARRO, Dondee; TAKEDA, Youichi; MIURA-MATTAUSCH, Mitiko et al.IEEE microwave and wireless components letters. 2006, Vol 16, Num 3, pp 125-127, issn 1531-1309, 3 p.Article

Compact Modeling of Expansion Effects in LDMOSHZUKA, Takahiro; SAKUDA, Takashi; ORITSUKI, Yasunori et al.IEICE transactions on electronics. 2012, Vol 95, Num 11, pp 1817-1823, issn 0916-8524, 7 p.Article

A carrier-transit-delay-based nonquasi-static MOSFET model for circuit simulation and its application to harmonic distortion analysisNAVARRO, Dondee; TAKEDA, Youichi; MIYAKE, Masataka et al.I.E.E.E. transactions on electron devices. 2006, Vol 53, Num 9, pp 2025-2034, issn 0018-9383, 10 p.Article

Completely surface-potential-based compact model of the fully depleted SOI-MOSFET including short-channel effectsSADACHIKA, Norio; KITAMARU, Daisuke; UETSUJI, Yasuhito et al.I.E.E.E. transactions on electron devices. 2006, Vol 53, Num 9, pp 2017-2024, issn 0018-9383, 8 p.Article

Quasi-2-Dimensional Compact Resistor Model for the Drift Region in High-Voltage LDMOS DevicesTANAKA, Akihiro; ORITSUKI, Yasunori; KIKUCHIHARA, Hideyuki et al.I.E.E.E. transactions on electron devices. 2011, Vol 58, Num 7, pp 2072-2080, issn 0018-9383, 9 p.Article

HiSIM-HV: A Compact Model for Simulation of High-Voltage MOSFET CircuitsORITSUKI, Yasunori; YOKOMICHI, Masahiro; MIURA-MATTAUSCH, Mitiko et al.I.E.E.E. transactions on electron devices. 2010, Vol 57, Num 10, pp 2671-2678, issn 0018-9383, 8 p.Article

A compact model of the pinch-off region of 100 nm MOSFETs based on the surface-potentialNAVARRO, Dondee; MIZOGUCHI, Takeshi; NAKAYAMA, Noriaki et al.IEICE transactions on electronics. 2005, Vol 88, Num 5, pp 1079-1086, issn 0916-8524, 8 p.Article

Non-Quasi-Static Carrier Dynamics of MOSFETs under Low-Voltage Operation : Fundamentals and applications of advanced semiconductor devicesMIYAKE, Masataka; HORI, Daisuke; TSUKADA, Toshiro et al.IEICE transactions on electronics. 2009, Vol 92, Num 5, pp 608-615, issn 0916-8524, 8 p.Article

1/f-noise characteristics in 100 nm-MOSFETs and its modeling for circuit simulationMATSUMOTO, Shizunori; UENO, Hiroaki; NAKAYAMA, Noriaki et al.IEICE transactions on electronics. 2005, Vol 88, Num 2, pp 247-254, issn 0916-8524, 8 p.Article

Modeling of NBTI Stress Induced Hole-Trapping and Interface-State-Generation Mechanisms under a Wide Range of Bias ConditionsCHENYUE MA; MATTAUSCH, Hans Jürgen; MIURA-MATTAUSCH, Mitiko et al.IEICE transactions on electronics. 2013, Vol 96, Num 10, pp 1339-1347, issn 0916-8524, 9 p.Article

HiSIM2 : Advanced MOSFET model valid for RF circuit simulationMIURA-MATTAUSCH, Mitiko; SADACHIKA, Norio; MATTAUSCH, Hans Jürgen et al.I.E.E.E. transactions on electron devices. 2006, Vol 53, Num 9, pp 1994-2007, issn 0018-9383, 14 p.Article