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Patterning of narrow porous SiOCH trenches using a TiN hard maskDARNON, M; CHEVOLLEAU, T; TORRES, J et al.Microelectronic engineering. 2008, Vol 85, Num 11, pp 2226-2235, issn 0167-9317, 10 p.Article

Process optimisation and dual damascene integration of porous CVD SiOC dielectric at 2.4 and 2.2 k-values for 45 nm CMOS technologyARNAL, V; HOOFMAN, R. J. O. M; DAAMEN, R et al.IEEE international interconnect technology conference. 2004, pp 202-204, isbn 0-7803-8308-7, 1Vol, 3 p.Conference Paper

Efficiency of reducing and oxidizing ash plasmas in preventing metallic barrier diffusion into porous SiOCHPOSSEME, N; CHEVOLLEAU, T; JOUBERT, O et al.Microelectronic engineering. 2008, Vol 85, Num 8, pp 1842-1849, issn 0167-9317, 8 p.Article

Impact of patterning and ashing on electrical properties and reliability of interconnects in a porous SiOCH ultra low-k dielectric materialAIMADEDDINE, M; ARNAL, V; TORRES, J et al.Microelectronic engineering. 2005, Vol 82, Num 3-4, pp 341-347, issn 0167-9317, 7 p.Conference Paper

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