Systolic counters with unique zero stateSTAN, Mircea R.IEEE International Symposium on Circuits and Systems. 2004, pp 909-912, isbn 0-7803-8251-X, 4 p.Conference Paper

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Design of efficient modulo 2ⁿ + 1 multipliersVERGOS, H. T; EFSTATHIOU, C.IET computers & digital techniques (Print). 2007, Vol 1, Num 1, pp 49-57, issn 1751-8601, 9 p.Article

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