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Results 1 to 25 of 162268

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Macro-modeling concepts for the chip electrical interfaceAMICK, Brian W; GAUTHIER, Claude R; LIU, Dean et al.Design automation conference. 2002, pp 391-394, isbn 1-58113-461-4, 4 p.Conference Paper

Fast and accurate behavioral simulation of fractional-n frequency synthesizers and other PLL/DLL circuitsPERROTT, Michael H.Design automation conference. 2002, pp 498-503, isbn 1-58113-461-4, 6 p.Conference Paper

IP delivery for FPGAs using applets and JHDLWIRTHLIN, Michael J; MCMURTREY, Brian.Design automation conference. 2002, pp 2-7, isbn 1-58113-461-4, 6 p.Conference Paper

Carbon nanotube field-effect transistors and logic circuitsMARTEL, R; DERVCKE, V; APPENZELLER, J et al.Design automation conference. 2002, pp 94-98, isbn 1-58113-461-4, 5 p.Conference Paper

VeriCDF: A new verification methodology for charged device failuresLEE, Jaesik; KIM, Ki-Wook; KANG, Sung-Mo et al.Design automation conference. 2002, pp 874-879, isbn 1-58113-461-4, 6 p.Conference Paper

On metrics for comparing routability estimation methods for FPGAsKANNAN, Parivallal; BALACHANDRAN, Shankar; BHATIA, Dinesh et al.Design automation conference. 2002, pp 70-75, isbn 1-58113-461-4, 6 p.Conference Paper

DRG-cache: A data retention gated-ground cache for low powerAGARWAL, Amit; HAI LI; ROY, Kaushik et al.Design automation conference. 2002, pp 473-478, isbn 1-58113-461-4, 6 p.Conference Paper

Reduction of SOC test data volume, scan power and testing time using alternating run-length codesCHANDRA, Anshuman; CHAKRABARTY, Krishnendu.Design automation conference. 2002, pp 669-672, isbn 1-58113-461-4, 4 p.Conference Paper

Implementing asynchronous circuits using a conventional EDA tool-flowSOTIRIOU, Christos P.Design automation conference. 2002, pp 415-418, isbn 1-58113-461-4, 4 p.Conference Paper

The next chip challenge: Effective methods for viable mixed technology SoCsBERNHARD POGGE, H.Design automation conference. 2002, pp 84-87, isbn 1-58113-461-4, 4 p.Conference Paper

Self-referential verification of gate-level implementations of arithmetic circuitsCHANG, Ying-Tsai; CHENG, Kwang-Ting.Design automation conference. 2002, pp 311-316, isbn 1-58113-461-4, 6 p.Conference Paper

Transformation rules for designing CNOT-based quantum circuitsIWAMA, Kazuo; KAMBAYASHI, Yahiko; YAMASHITA, Shigeru et al.Design automation conference. 2002, pp 419-424, isbn 1-58113-461-4, 6 p.Conference Paper

Osculating thevenin model for predicting delay and slew of capacitively characterized cellsSHEEHAN, Bernard N.Design automation conference. 2002, pp 866-869, isbn 1-58113-461-4, 4 p.Conference Paper

An implication-based method to detect multi-cycle paths in large sequential circuitsHIGUCHI, Hiroyuki.Design automation conference. 2002, pp 164-169, isbn 1-58113-461-4, 6 p.Conference Paper

Combined BEM/FEM substrate resistance modelingSCHRIK, E; VAN DER MEIIS, N. P.Design automation conference. 2002, pp 771-776, isbn 1-58113-461-4, 6 p.Conference Paper

Life is CMOS: Why chase the life after?SERY, George; BORKAR, Shekhar; DE, Vivek et al.Design automation conference. 2002, pp 78-83, isbn 1-58113-461-4, 6 p.Conference Paper

On the complexity of encoding in analog circuitsWEGENER, I.Information processing letters. 1996, Vol 60, Num 1, pp 49-52, issn 0020-0190Article

Quantum circuits with unbounded fan-outHØYER, Peter; SPALEK, Robert.Lecture notes in computer science. 2003, pp 234-246, issn 0302-9743, isbn 3-540-00623-0, 13 p.Conference Paper

An optimized S-Box circuit architecture for low power AES designMORIOKA, Sumio; SATOH, Akashi.Lecture notes in computer science. 2002, pp 172-186, issn 0302-9743, isbn 3-540-00409-2, 15 p.Conference Paper

Mapping the effect of a circuit impedance on the common-mode excitation of electromagnetic interferenceJERSE, Thomas A.IEEE SoutheastCon conference. 2002, pp 104-107, isbn 0-7803-7252-2, 4 p.Conference Paper

A fast, inexpensive and scalable hardware acceleration technique for functional simulationCADAMBI, Srihari; MULPURI, Chandra S; ASHAR, Pranav N et al.Design automation conference. 2002, pp 566-569, isbn 1-58113-461-4, 4 p.Conference Paper

A general probabilistic framework for worst case timing analysisORSHANSKY, Michael; KEUTZER, Kurt.Design automation conference. 2002, pp 552-555, isbn 1-58113-461-4, 4 p.Conference Paper

Optimal group gossiping in hypercubes under a circuit-switching modelFUJITA, S; YAMASHITA, M.SIAM journal on computing (Print). 1996, Vol 25, Num 5, pp 1045-1060, issn 0097-5397Article

Tantrix rotation puzzles are intractableHOLZER, Markus; HOLZER, Waltraud.Discrete applied mathematics. 2004, Vol 144, Num 3, pp 345-358, issn 0166-218X, 14 p.Conference Paper

Assembling strategies in extrinsic evolvable hardware with bidirectional incremental evolutionBARADAVKA, Igor; KALGANOVA, Tatiana.Lecture notes in computer science. 2003, pp 276-285, issn 0302-9743, isbn 3-540-00971-X, 10 p.Conference Paper

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