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Negation-Limited Inverters of Linear Size : Foundations of Computer ScienceMORIZUMI, Hiroki; SUZUKI, Genki.IEICE transactions on information and systems. 2010, Vol 93, Num 2, pp 257-262, issn 0916-8532, 6 p.Article

A note on dimensions of polynomial size circuitsXIAOYANG GU.Theoretical computer science. 2006, Vol 359, Num 1-3, pp 176-187, issn 0304-3975, 12 p.Article

Bounded-width polynomial-size Boolean formulas compute exactly those functions in AC0ISTRAIL, S; ZIVKOVIC, D.Information processing letters. 1994, Vol 50, Num 4, pp 211-216, issn 0020-0190Article

A well-mixed function with circuit complexity 5n: Tightness of the Lachish―Raz-type boundsAMANO, Kazuyuki; JUN TARUI.Theoretical computer science. 2011, Vol 412, Num 18, pp 1646-1651, issn 0304-3975, 6 p.Conference Paper

Linear-size log-depth negation-limited inverter for k-tonic binary sequencesMORIZUMI, Hiroki; TARUI, Jun.Theoretical computer science. 2009, Vol 410, Num 11, pp 1054-1060, issn 0304-3975, 7 p.Conference Paper

Limiting negations in non-deterministic circuitsMORIZUMI, Hiroki.Theoretical computer science. 2009, Vol 410, Num 38-40, pp 3988-3994, issn 0304-3975, 7 p.Article

Bounds on an exponential sum arising in Boolean circuit complexityGREEN, Frederic; ROY, Amitabha; STRAUBING, Howard et al.Comptes rendus. Mathématique. 2005, Vol 341, Num 5, pp 279-282, issn 1631-073X, 4 p.Article

A low-power decimation filter for a sigma-delta converter based on a power-optmized sinc filterGEROSA, Andrea; NEVIANI, Andrea.IEEE International Symposium on Circuits and Systems. 2004, pp 245-248, isbn 0-7803-8251-X, 4 p.Conference Paper

High performance viterbi decoder using modified register exchange methodsHAN, Jae-Sun; KIM, Tae-Jin; LEE, Chanho et al.IEEE International Symposium on Circuits and Systems. 2004, pp 553-556, isbn 0-7803-8251-X, 4 p.Conference Paper

Functional complexity estimation for large combinational circuitsABORHEY, S.IEE proceedings. Computers and digital techniques. 2002, Vol 149, Num 2, pp 39-45, issn 1350-2387Article

Combinational ae-af system with fuzzy climbing search servoCHEN, Chao-Yeh; TSENG, Chen-Yu; HUNG, Chi-Hsuan et al.Proceedings of SPIE, the International Society for Optical Engineering. 2006, pp 60690B.1-60690B.8, issn 0277-786X, isbn 0-8194-6109-1, 1VolConference Paper

An optimal parallel algorithm for formula evaluationBUSS, S; COOK, S; GUPTA, A et al.SIAM journal on computing (Print). 1992, Vol 21, Num 4, pp 755-780, issn 0097-5397Article

A superpolynomial lower bound for a circuit computing the clique function with at most (1/6) log log n negation gatesAMANO, Kazuyuki; MARUOKA, Akira.SIAM journal on computing (Print). 2006, Vol 35, Num 1, pp 201-216, issn 0097-5397, 16 p.Article

Multi-Linear Formulas for Permanent and Determinant Are of Super-Polynomial SizeRAZ, Ran.Journal of the Association for Computing Machinery. 2009, Vol 56, Num 2, issn 0004-5411, 8.1-8.17Article

On the negation-limited circuit complexity of mergingAMANO, Kazuyuki; MARUOKA, Akira; TARUI, Jun et al.Discrete applied mathematics. 2003, Vol 126, Num 1, pp 3-8, issn 0166-218X, 6 p.Conference Paper

Reductions for monotone Boolean circuitsIWAMA, Kazuo; MORIZUMI, Hiroki; TARUI, Jun et al.Theoretical computer science. 2008, Vol 408, Num 2-3, pp 208-212, issn 0304-3975, 5 p.Article

The computational power of Benenson automataSOLOVEICHIK, David; WINFREE, Erik.Theoretical computer science. 2005, Vol 344, Num 2-3, pp 279-297, issn 0304-3975, 19 p.Article

A lower bound method for quantum circuitsBERA, Debajyoti.Information processing letters. 2011, Vol 111, Num 15, pp 723-726, issn 0020-0190, 4 p.Article

Tight bounds for the multiplicative complexity of symmetric functionsBOYAR, Joan; PERALTA, René.Theoretical computer science. 2008, Vol 396, Num 1-3, pp 223-246, issn 0304-3975, 24 p.Article

DEFINABILITY OF LANGUAGES BY GENERALIZED FIRST-ORDER FORMULAS OVER (N, +)ROY, Amitabha; STRAUBING, Howard.SIAM journal on computing (Print). 2008, Vol 37, Num 2, pp 502-521, issn 0097-5397, 20 p.Article

Energy reduction of the fetch mechanism through dynamic adaptationDEL PINO, S; CHAVER, D; PINUEL, L et al.IET computers & digital techniques (Print). 2008, Vol 2, Num 2, pp 94-107, issn 1751-8601, 14 p.Article

Hardware-efficient FIR filters with reduced adder stepMASKELL, D. L; LIEWO, J.Electronics Letters. 2005, Vol 41, Num 22, pp 1211-1213, issn 0013-5194, 3 p.Article

New upper bounds on the Boolean circuit complexity of symmetric functionsDEMENKOV, E; KOJEVNIKOV, A; KULIKOV, A et al.Information processing letters. 2010, Vol 110, Num 7, pp 264-267, issn 0020-0190, 4 p.Article

Mixed polarity reversible Peres gatesMORAGA, C.Electronics letters. 2014, Vol 50, Num 14, pp 987-989, issn 0013-5194, 3 p.Article

A Novel Methodology to Reduce Leakage Power in CMOS Complementary CircuitsLAKSHMIKANTHAN, Preetham; NUNEZ, Adrian.Lecture notes in computer science. 2006, pp 614-623, issn 0302-9743, isbn 3-540-39094-4, 1Vol, 10 p.Conference Paper

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