Intégration d'un raisonnement sur les symétries dans une procédure DPLL = Integration of reasoning on symmetry in the DPLL procedureCHU MIN LI; JURKOWIAK, Bernard; PURDOM, Paul W et al.Journées nationales sur la résolution pratique de problèmes NP-complets. 2002, pp 273-274, isbn 2-7261-1208-0, 2 p.Conference Paper

Clock Multiplication Techniques Using Digital Multiplying Delay-Locked LoopsELSHAZLY, Amr; INTI, Rajesh; YOUNG, Brian et al.IEEE journal of solid-state circuits. 2013, Vol 48, Num 6, pp 1416-1428, issn 0018-9200, 13 p.Article

A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling TechniqueHYUNG SEOK KIM; ORNELAS, Carlos; CHANDRASHEKAR, Kailash et al.IEEE journal of solid-state circuits. 2013, Vol 48, Num 7, pp 1721-1729, issn 0018-9200, 9 p.Conference Paper

MaxSolver: An efficient exact algorithm for (weighted) maximum satisfiabilityZHAO XING; WEIXIONG ZHANG.Artificial intelligence. 2005, Vol 164, Num 1-2, pp 47-80, issn 0004-3702, 34 p.Article

A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur CancellationZANUSO, Marzo; LEVANTINO, Salvatore; SAMORI, Carlo et al.IEEE journal of solid-state circuits. 2011, Vol 46, Num 3, pp 627-638, issn 0018-9200, 12 p.Article

A 2.9-4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fs_rms Integrated Jitter at 4.5-mW PowerTASCA, Davide; ZANUSO, Marco; MARZIN, Giovanni et al.IEEE journal of solid-state circuits. 2011, Vol 46, Num 12, pp 2745-2758, issn 0018-9200, 14 p.Conference Paper

A 5.6 GHz to 11.5 GHz DCO for Digital Dual Loop CDRsTITUS, Ward S; KENNEY, John G.IEEE journal of solid-state circuits. 2012, Vol 47, Num 5, pp 1123-1130, issn 0018-9200, 8 p.Conference Paper

On the power of clause-learning SAT solvers as resolution enginesPIPATSRISAWAT, Knot; DARWICHE, Adnan.Artificial intelligence (General ed.). 2011, Vol 175, Num 2, pp 512-525, issn 0004-3702, 14 p.Article

Cutting to the Chase: Solving Linear Integer ArithmeticJOVANOVIC, Dejan; DE MOURA, Leonardo.Journal of automated reasoning. 2013, Vol 51, Num 1, pp 79-108, issn 0168-7433, 30 p.Article

A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With ―36 dB EVM at 5 mW PowerMARZIN, Giovanni; LEVANTINO, Salvatore; SAMORI, Carlo et al.IEEE journal of solid-state circuits. 2012, Vol 47, Num 12, pp 2974-2988, issn 0018-9200, 15 p.Conference Paper

Modelling and solving temporal reasoning as propositional satisfiabilityDUC NGHIA PHAM; THORNTON, John; SATTAR, Abdul et al.Artificial intelligence (General ed.). 2008, Vol 172, Num 15, pp 1752-1782, issn 0004-3702, 31 p.Article

Generalizing DPLL and satisfiability for equalitiesBADBAN, Bahareh; DE POL, Jaco Van; TVERETINA, Olga et al.Report - Software engineering. 2004, Num 7, pp 1-28, issn 1386-369X, 28 p.Article

The model evolution calculus as a first-order DPLL methodBAUMGARTNER, Peter; TINELLI, Cesare.Artificial intelligence. 2008, Vol 172, Num 4-5, pp 591-632, issn 0004-3702, 42 p.Article

Phase error dynamics of a class of DPLLs in presence of cochannel interferenceBANERJEE, T; SARKAR, B. C.Signal processing. 2005, Vol 85, Num 6, pp 1139-1147, issn 0165-1684, 9 p.Article

A new dynamic gain control algorithm for speed enhancement of digital-phase locked loops (DPLLs)BANERJEE, T; SARKAR, B. C.Signal processing. 2006, Vol 86, Num 7, pp 1426-1434, issn 0165-1684, 9 p.Article

A digital clock and data recovery architecture for multi-gigabit/s binary linksSONNTAG, Jeff L; STONICK, John.IEEE journal of solid-state circuits. 2006, Vol 41, Num 8, pp 1867-1875, issn 0018-9200, 9 p.Conference Paper

Phase error dynamics of a class of modified second-order digital phase-locked loops in the background of cochannel interferenceBANERJEE, Tanmoy; SARKAR, B. C.Signal processing. 2005, Vol 85, Num 8, pp 1611-1622, issn 0165-1684, 12 p.Article

Generalizing DPLL and satisfiability for equalitiesBADBAN, Bahareh; VAN DE POL, Jaco; TVERETINA, Olga et al.Information and computation (Print). 2007, Vol 205, Num 8, pp 1188-1211, issn 0890-5401, 24 p.Article

Formal verification of a modern SAT solver by shallow embedding into Isabelle/HOLMARIC, Filip.Theoretical computer science. 2010, Vol 411, Num 50, pp 4333-4356, issn 0304-3975, 24 p.Article

A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13 μm CMOS TechnologyJIANJUN YU; DAI, Fa Foster; JAEGER, Richard C et al.IEEE journal of solid-state circuits. 2010, Vol 45, Num 4, pp 830-842, issn 0018-9200, 13 p.Conference Paper

digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL ArchitectureNONIS, Roberto; GROLLITSCH, Werner; SANTA, Thomas et al.IEEE journal of solid-state circuits. 2013, Vol 48, Num 12, pp 3134-3145, issn 0018-9200, 12 p.Conference Paper

A Digital Phase-Locked Loop With Calibrated Coarse and Stochastic Fine TDCSAMARAH, Amer; AARUSONE, Anthony Chan.IEEE journal of solid-state circuits. 2013, Vol 48, Num 8, pp 1829-1841, issn 0018-9200, 13 p.Conference Paper

Joint Carrier Synchronization and Equalization Algorithm for Packet-Based OFDM Systems Over the Multipath Fading ChannelWU, Chih-Feng; SHIUE, Muh-Tian; WANG, Chorng-Kuang et al.IEEE transactions on vehicular technology. 2010, Vol 59, Num 1, pp 248-260, issn 0018-9545, 13 p.Article