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SPP photonic probe of damascene line qualityKNIGHT, Gary D; SMY, Tom J.Proceedings - Electrochemical Society. 2005, pp 206-217, issn 0161-6374, isbn 1-56677-464-0, 12 p.Conference Paper

Integrated multiscale process simulation of damascene structuresBLOOMFIELD, M. O; YEON HO IM; SEOK, Jongwon et al.Proceedings - Electrochemical Society. 2003, pp 455-466, issn 0161-6374, isbn 1-56677-376-8, 12 p.Conference Paper

90nm node damascene copper stress voiding model and lifetime extrapolation methodologyFEDERSPIEL, X; GRAIN, S.International Integrated Reliability Workshop. 2004, pp 64-70, isbn 0-7803-8517-9, 1Vol, 7 p.Conference Paper

Successful dual damascene integration of extreme low k materials (k < 2.0) using a novel gap fill based integration schemeNITTA, S; PURUSHOTHAMAN, S; LINIGER, E et al.International Electron Devices Meeting. 2004, pp 321-324, isbn 0-7803-8684-1, 1Vol, 4 p.Conference Paper

Layout dependency induced deviation from poisson area scaling in BEOL dielectric reliabilityLI, Y.-L; TÖKEI, Zs; ROUSSEL, Ph et al.Microelectronics and reliability. 2005, Vol 45, Num 9-11, pp 1299-1304, issn 0026-2714, 6 p.Conference Paper

A study of failure mechanism on the electromigration structure for the copper-coral backendKAMAT, Nitin R; LIM, James Y.International workshop on thermal investigations of ICs and systems. 2003, pp 55-58, isbn 2-84813-020-2, 1Vol, 4 p.Conference Paper

The study of sputtered RF Ta on the PID in Cu dual damascene technologyWEN HUI LU; KIM KENG TEO; CHAW SING HO et al.International Integrated Reliability Workshop. 2004, pp 158-161, isbn 0-7803-8517-9, 1Vol, 4 p.Conference Paper

Investigation of copper bath ageing in the damascene process by electrochemical impedance spectroscopyGABRIELLI, C; MOCOTEGUY, P; PERROT, H et al.Proceedings - Electrochemical Society. 2003, pp 129-136, issn 0161-6374, isbn 1-56677-390-3, 8 p.Conference Paper

Complementary sidewall-spacer-diffused ultrashallow SD extension process for damascene independently-double-gated SOI CMOSPARKE, S; GOLDSTON, M; HACKLER, D et al.IEEE international SOI conference. 2004, pp 104-105, isbn 0-7803-8497-0, 1Vol, 2 p.Conference Paper

Electrical characterization of crystalline Gd₂O₃gate dielectric MOSFETs fabricated by damascene metal gate technologyENDRES, Ralf; STEFANOV, Yordan; SCHWALKE, Udo et al.Microelectronics and reliability. 2007, Vol 47, Num 4-5, pp 528-531, issn 0026-2714, 4 p.Conference Paper

A novel sub-50 nm multi-bridge-channel MOSFET (MBCFET) with extremely high performanceLEE, Sung-Young; YOON, Eun-Jung; KIM, Dong-Won et al.Symposium on VLSI Technology. sd, pp 200-201, isbn 0-7803-8289-7, 1Vol, 2 p.Conference Paper

Design and fabrication of highly complex topographic nano-imprint template for dual damascene full 3-D imprintingMACDONALD, Susan; HUGHES, Greg; STEWART, Michael et al.Proceedings of SPIE, the International Society for Optical Engineering. 2005, issn 0277-786X, isbn 0-8194-6014-1, 2Vol, Part 1, 59922F.1-59922F.9Conference Paper

Copper corrosion issue and analysis on copper damascene processSONG, Z. G; NEO, S. P; OH, C. K et al.International Symposium on the Physical & Failure Analysis of Integrated Circuits. 2004, pp 71-74, isbn 0-7803-8454-7, 1Vol, 4 p.Conference Paper

The effect of FSG stability at high temperature on stress-induced voiding in Cu dual-damascene interconnectsOH, Hyeok-Sang; CHUNG, Juhyuk; LEE, Jung-Woo et al.IEEE international interconnect technology conference. 2004, pp 21-23, isbn 0-7803-8308-7, 1Vol, 3 p.Conference Paper

Growth and integration challenges for carbon nanotube interconnectsVANPAEMEL, Johannes; SUGIURA, Masahito; BARBARIN, Yohan et al.Microelectronic engineering. 2014, Vol 120, pp 188-193, issn 0167-9317, 6 p.Conference Paper

Mechanical Stress Influence on Electronic Transport in Low-k SiOC Dielectric Dual Damascene CapacitorYANG, Ya-Liang; YOUNG, Tai-Fa; CHANG, Ting-Chang et al.IEEE electron device letters. 2013, Vol 34, Num 8, pp 1056-1058, issn 0741-3106, 3 p.Article

Cu Single Damascene Integration of an Organic Nonporous Ultralow-k Fluorocarbon Dielectric Deposited by Microwave-Excited Plasma-Enhanced CVDXUN GU; NEMOTO, Takenao; TOMITA, Yugo et al.I.E.E.E. transactions on electron devices. 2012, Vol 59, Num 5, pp 1445-1453, issn 0018-9383, 9 p.Article

High-Density 3-D Interconnect of Cu―Cu Contacts With Enhanced Contact Resistance by Self-Assembled Monolayer (SAM) PassivationLAN PENG; HONGYU LI; DAU FATT LIM et al.I.E.E.E. transactions on electron devices. 2011, Vol 58, Num 8, pp 2500-2506, issn 0018-9383, 7 p.Article

Spacer defined double patterning for (sub-)20nm half pitch single damascene structuresVERSLUIJS, Janko; YONG KONG SIEW; KUNNEN, Eddy et al.Proceedings of SPIE, the International Society for Optical Engineering. 2011, Vol 7973, issn 0277-786X, isbn 978-0-8194-8532-8, 79731R.1-79731R.11, 2Conference Paper

Variable-shaped e-beam lithography enabling process development for future copper damascene technologyJASCHINSKY, Philipp; ERBEN, Jens-Wolfram; GESSNER, Thomas et al.Microelectronic engineering. 2011, Vol 88, Num 8, pp 1978-1981, issn 0167-9317, 4 p.Conference Paper

Copper―dielectric cap interface with enhanced reliability for 45 nm technology and beyondHOHAGE, J; MAYER, U; LEHR, M. U et al.Microelectronic engineering. 2010, Vol 87, Num 11, pp 2119-2123, issn 0167-9317, 5 p.Article

Total Performance of 32-nm-Node Ultralow-k/Cu Dual-Damascene Interconnects Featuring Short-TAT Silylated Porous Silica (k = 2.1)ODA, Noriaki; CHIKAKI, Shinichi; HAYASHI, Ryo et al.I.E.E.E. transactions on electron devices. 2010, Vol 57, Num 11, pp 2821-2830, issn 0018-9383, 10 p.Article

A modified Damascene electrodeposition process for bottom-up filling of recessed surface featuresCHANG HWA LEE; MOFFAT, Thomas P.Electrochimica acta. 2010, Vol 55, Num 28, pp 8527-8531, issn 0013-4686, 5 p.Article

Reliability of copper low-k interconnectsTOKEI, Zsolt; CROES, Kristof; BEYER, Gerald P et al.Microelectronic engineering. 2010, Vol 87, Num 3, pp 348-354, issn 0167-9317, 7 p.Conference Paper