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STTE/EF-2000 typhoon new generation of automatic test bench (STTEs) for eurofighter's avionic unitsTORDESILLAS, Javier; MUNOZ, Fernando.IEEE instrumentation & measurement magazine. 2007, Vol 10, Num 4, pp 15-19, issn 1094-6969, 5 p.Conference Paper

Unit testing using design by contract and equivalence partitionsMADSEN, Per.Lecture notes in computer science. 2003, pp 425-426, issn 0302-9743, isbn 3-540-40215-2, 2 p.Conference Paper

A strategy for using genetic algorithms to automate branch and fault-based testingJONES, B. F; EYRES, D. E; STHAMER, H.-H et al.Computer journal (Print). 1998, Vol 41, Num 2, pp 98-107, issn 0010-4620Article

Reducing the number of specified values per test vector by increasing the test set sizePOMERANZ, I; REDDY, S. M.IEE proceedings. Computers and digital techniques. 2006, Vol 153, Num 1, pp 39-46, issn 1350-2387, 8 p.Article

Theory and practice of automatic design constraint generationBHADRA, J.IEE proceedings. Computers and digital techniques. 2006, Vol 153, Num 1, pp 9-19, issn 1350-2387, 11 p.Article

An automatic test data generation system based on the integrated classification-tree methodologyCAIN, Andrew; TSONG YUEH CHEN; GRANT, Doug et al.Lecture notes in computer science. 2004, pp 225-238, issn 0302-9743, isbn 3-540-21975-7, 14 p.Conference Paper

Using model checking to generate tests from requirements specificationsGARGANTINI, A; HEITMEYER, C.Lecture notes in computer science. 1999, pp 146-162, issn 0302-9743, isbn 3-540-66538-2Conference Paper

Test de spécifications de services de télécommunication = Testing formal telecommunication feature specificationsZuanon, Nicolas; Ouabdesselam, Farid.2000, 214 p.Thesis

Efficient identification of crosstalk induced slowdown targetsBREUER, Melvin A; GUPTA, Sandeep K; NAZARIAN, Shahin et al.Asian test symposium. 2004, pp 124-131, isbn 0-7695-2235-1, 1Vol, 8 p.Conference Paper

Automatic testing of real-time systemsNIELSEN, Brian.Modeling and verification of parallel processes. Summer school. 2001, pp 3-43, 41 p.Conference Paper

Development of lexico-grammar resources for natural language generation (experience from AGILE project)STAYKOVA, Kamenka; DOCHEV, Danail.Lecture notes in computer science. 2000, pp 242-251, issn 0302-9743, isbn 3-540-41044-9Conference Paper

Fast fault translationVINNAKOTA, B; ANDREWS, J.IEEE transactions on very large scale integration (VLSI) systems. 1998, Vol 6, Num 1, pp 122-133, issn 1063-8210Article

Design for hierarchical testability of RTL circuits obtained by behavioral synthesisGHOSH, I; RAGHUNATHAN, A; JHA, N. K et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1997, Vol 16, Num 9, pp 1001-1014, issn 0278-0070Article

Application of two test generation tools to an industrial case studyCAVALLI, Ana; MAAG, Stephane; MALLOULI, Wissam et al.Lecture notes in computer science. 2006, pp 134-148, issn 0302-9743, isbn 3-540-34184-6, 1Vol, 15 p.Conference Paper

An optimized DFT and test pattern generation strategy for an intel high performance microprocessorWU, David M; MIKE LIN; REDDY, Madhukar et al.International Test Conference. 2004, pp 38-47, isbn 0-7803-8580-2, 1Vol, 10 p.Conference Paper

ALAPTF : A new transition fault model and the ATPG algorithmGUPTA, Puncet; HSIAO, Michael S.International Test Conference. 2004, pp 1053-1060, isbn 0-7803-8580-2, 1Vol, 8 p.Conference Paper

Mise en oeuvre du profil de test d'UML et élaboration de jeux de test exécutables = Implementation of UML test profile and generation of test setLEBLANC, Philippe; GUEVEL, Jean-Marc.Génie logiciel (1995). 2003, Num 67, pp 37-41, issn 1265-1397, 5 p.Article

Identifying invalid states for sequential circuit test generationLIANG, H.-C; CHUNG LEN LEE; CHEN, J. E et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1997, Vol 16, Num 9, pp 1025-1033, issn 0278-0070Article

A new script language applicable to symbolic execution systemsKOUTSIKAS, C; MALEVRIS, N.International journal of computers & applications. 2006, Vol 28, Num 1, pp 1-11, issn 1206-212X, 11 p.Article

Minimizing power consumption in scan testing : Pattern generation and DFT techniquesBUTLER, Kenneth M; SAXENA, Jayashree; FRYARS, Tony et al.International Test Conference. 2004, pp 355-364, isbn 0-7803-8580-2, 1Vol, 10 p.Conference Paper

Des indicateurs pour le suivi et l'évaluation des phases d'essais des logiciels = Indicators for the monitoring and evaluation of software test phasesCLERY, Jérome E; RAGOT, Alain N; VALLEE, Frédérique E et al.Génie logiciel (1995). 2003, Num 67, pp 42-47, issn 1265-1397, 6 p.Article

A genetic algorithm framework for test generationRUDNICK, E. M; PATEL, J. H; GREENSTEIN, G. S et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1997, Vol 16, Num 9, pp 1034-1044, issn 0278-0070Article

Test et diagnostic des cartes et des MCMs partiellement Boundary Scan = Test and diagnosis of partially Boundary Scan boards and MCMsTouati, Mohamed Hédi; Courtois, B.1996, 130 p.Thesis

Apport d'un prototype spécifié en Z dans le redéveloppement d'un outil de test = Using a Z specification as a prototype in a redevelopment projectLEDRU, Yves; DU BOUSQUET, Lydie.TSI. Technique et science informatiques. 2012, Vol 31, Num 6, pp 743-767, issn 0752-4072, 25 p.Conference Paper

Program slicing for ATPG-based property checkingVEDULA, Vivekananda M; TOWNSEND, Whitney J; ABRAHAM, Jacob A et al.International Conference on Embedded Systems DesignInternational Conference on VLSI Design. 2004, pp 591-596, isbn 0-7695-2072-3, 1Vol, 6 p.Conference Paper

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