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Results 1 to 25 of 18001

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Balancing electrical and optical interconnection resources at low levelsDRABIK, T. J.SPIE proceedings series. 1998, pp 556-559, isbn 0-8194-2949-XConference Paper

Multilevel interconnect technology (Austin TX, 1-2 October 1997)Patel, Divyesh N; Graef, Mart.SPIE proceedings series. 1997, isbn 0-8194-2546-X, VII, 132 p, isbn 0-8194-2546-XConference Proceedings

Embeddings among meshes and toriMA, E; LIXIN TAO.Journal of parallel and distributed computing (Print). 1993, Vol 18, Num 1, pp 44-55, issn 0743-7315Article

UNE NOUVELLE TECHNIQUE D'INTERCONNEXION MULTICOUCHE.KOCSIS A.1975; ELECTRON. MICROELECTRON. INDUSTR.; FR.; DA. 1975; NO 209 SUPPL.; PP. 32-63 (4P.); MEME DOC. ANGLArticle

MULTILAYER INTERCONNECTION TECHNIQUES APPLIED TO HIGH SPEED COMPUTER SYSTEMS.BINGHAM KC; NAYLOR R.1974; I.E.E.E. TRANS. PARTS HYBR. PACKAG.; U.S.A.; DA. 1974; VOL. 10; NO 3; PP. 175-180; BIBL. 3 REF.; (ELECTRON. COMPONENTS CONF.; WASHINGTON; 1974)Conference Paper

Interconnections and shattered illusionsKIELMAS, Maria.Petroleum review (London. 1968). 2011, Vol 65, Num 774, issn 0020-3076, 36-37, 40 [3 p.]Article

Comparison of system size for some optical interconnection architectures and the folded multi-facet architectureOZAKTAS, H. M; AMITAI, Y; GOODMAN, J. W et al.Optics communications. 1991, Vol 82, Num 3-4, pp 225-228, issn 0030-4018Article

PACKAGE DEVELOPMENT FOR A LARGE MULTI-CHIP ARRAY.CLEFORD AP; PAYNE JR.1974; ELECTRON. PACKAG. PRODUCT.; U.S.A.; DA. 1974; VOL. 14; NO 9; PP. 47-54 (4P.); BIBL. 6 REF.Article

INTERCONNEXION MULTICOUCHE PLANAR POUR CIRCUITS INTEGRES BIPOLAIRES DE GRANDE SURFACE.RIOULT JP; FABIEN R; GRIOT D et al.1974; DGRST-7371327; FR.; DA. 1974; PP. 1-12; (RAPP. FINAL, ACTION CONCERTEE: C.C.M.)Report

Design and implementation of a four-stage clustered free-space optical interconnectLACROIX, F; ROBERTSON, B; AYLIFFE, M. H et al.SPIE proceedings series. 1998, pp 107-110, isbn 0-8194-2949-XConference Paper

THICK-FILM PASTES FOR MULTILAYER USEKURZWEIL K; LOUGHRAN J.1973; SOLID-STATE TECHNOL.; U.S.A.; DA. 1973; VOL. 16; NO 5; PP. 36-42; BIBL. 14 REF.Serial Issue

SHIELDED SILICON GATE COMPLEMENTARY MOS INTEGRATED CIRCUITHUNG CHANG LIN; HALSOR JL; HAYES PJ et al.1972; I.E.E.E. TRANS. ELECTRON DEVICES; U.S.A.; DA. 1972; VOL. 19; NO 11; PP. 1199-1207; BIBL. 6 REF.Serial Issue

Routing algorithms for cellular interconnection arraysORUC, A. Y; DEEPAK PRAKASH.IEEE transactions on computers. 1984, Vol 33, Num 10, pp 939-942, issn 0018-9340Article

Optical interconnection based symbolic manipulationsCAULFIELD, H. J.Optical engineering (Bellingham. Print). 1986, Vol 25, Num 10, pp 1179-1180, issn 0091-3286Article

A parametric study of the attenuation constant of lossy microstrip linesVAKANAS, L. P; CANGELLARIS, A. C; PRINCE, J. L et al.IEEE transactions on microwave theory and techniques. 1990, Vol 38, Num 8, pp 1136-1139, issn 0018-9480, 4 p.Article

High performance polymers for packaging and interconnections in microelectronicsBUREAU, J.-M; BERNARD, F; BROUSSOUX, D et al.Revue technique - Thomson-CSF. 1989, Vol 20-21, Num 4, pp 689-724, issn 0035-4279Article

Interconnexions holographiques reconfigurables dans un cristal photoréfractif et applications aux réseaux de neurones = Reconfigurable holographic interconnections in a photorefractive crystal and applications to neural networksAing, Phannara; Roosen, G.1996, 221 p.Thesis

Local interconnection neural network and its optical implementationJIAJUN ZHANG; LI ZHANG; DAPEN YAN et al.Optics communications. 1993, Vol 102, Num 1-2, pp 13-20, issn 0030-4018Article

Fan-in and fan-out with optical interconnectionsGOODMAN, J. W.Optica acta. 1985, Vol 32, Num 12, pp 1489-1496, issn 0030-3909Article

Multilevel interconnect technology II (Santa Clara CA, 23-24 September 1998)Graef, Mart; Patel, Divyesh N.SPIE proceedings series. 1998, isbn 0-8194-2967-8, VII, 224 p, isbn 0-8194-2967-8Conference Proceedings

Interconnecting local networks to long-distance networksSCHNEIDEWIND, N. F.Computer (Long Beach, CA). 1983, Vol 16, Num 9, pp 15-24, issn 0018-9162Article

Solder bump height dependence of Josephson chip-to-card interconnection inductance using flip-chip bonding techniqueTEMMYO, J; AOKI, K; YOSHIKIYO, H et al.Journal of applied physics. 1983, Vol 54, Num 9, pp 5282-5286, issn 0021-8979Article

Design of multistage interconnection networksSOOD, A. K.IEE proceedings. Part E. Computers and digital techniques. 1983, Vol 130, Num 4, pp 109-115, issn 0143-7062Article

Latency requirements of optical interconnects at different memory hierarchy levels of a computer systemNEEFS, H; VAN HEUVEN, P; VAN CAMPENHOUT, J et al.SPIE proceedings series. 1998, pp 552-555, isbn 0-8194-2949-XConference Paper

Hybrid integration of a semiconductor optical amplifier for high throughput optical packet switched interconnection networksLIBOIRON-LADOUCEUR, Odile; BERGMAN, Keren.Proceedings of SPIE, the International Society for Optical Engineering. 2006, pp 63433G.1-63433G.5, issn 0277-786X, isbn 0-8194-6428-7Conference Paper

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