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Design of wallace tree multiplier and other components of a quantum ALU using reversible TSG gateTHAPLIYAL, Himanshu; SRINIVAS, M. B.Proceedings of SPIE, the International Society for Optical Engineering. 2006, pp 62640H.1-62640H.11, issn 0277-786X, isbn 0-8194-6329-9, 1VolConference Paper

Abstract passive interferometers with applications to conservative logicLEI QIAN; CAULFIELD, H. John.Optik (Stuttgart). 2005, Vol 116, Num 8, pp 404-408, issn 0030-4026, 5 p.Article

Improved Cost Reversible Multiplier DesignCUTITARU, Mihail; BELFORE, Lee A.Computer design. International conferenceWorldComp'2011. 2011, pp 35-38, isbn 1-60132-173-2, 4 p.Conference Paper

Novel design of a fast reversible Wallace sign multiplier circuit in nanotechnologyEHSAN POUR ALI AKBAR; HAGHPARAST, Majid; NAVI, Keivan et al.Microelectronics journal. 2011, Vol 42, Num 8, pp 973-981, issn 0959-8324, 9 p.Article

All-Optical Ultrafast Switching in 2 × 2 Silicon Microring Resonators and its Application to Reconfigurable DEMUX/MUX and Reversible Logic GatesSETHI, Purnima; ROY, Sukhdev.Journal of lightwave technology. 2014, Vol 32, Num 9-12, pp 2173-2180, issn 0733-8724, 8 p.Article

Approach to design a compact reversible low power binary comparatorHASAN BABU, Hafiz Md; SALEHEEN, Nazir; JAMAL, Lafifa et al.IET computers & digital techniques (Print). 2014, Vol 8, Num 3, pp 129-139, issn 1751-8601, 11 p.Article

Energy recovery circuits using reversible and partially reversible logicYE, Y; ROY, K.IEEE transactions on circuits and systems. 1, Fundamental theory and applications. 1996, Vol 43, Num 9, pp 769-778, issn 1057-7122Article

Design of Testable Reversible Sequential CircuitsTHAPLIYAL, Himanshu; RANGANATHAN, Nagarajan; KOTIYAL, Saurabh et al.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 7, pp 1201-1209, issn 1063-8210, 9 p.Article

A library-based synthesis methodology for reversible logicSAEEDI, Mehdi; SEDIGHI, Mehdi; MORTEZA SAHEB ZAMANI et al.Microelectronics journal. 2010, Vol 41, Num 4, pp 185-194, issn 0959-8324, 10 p.Article

Majority-based reversible logic gatesGUOWU YANG; HUNG, William N. N; XIAOYU SONG et al.Theoretical computer science. 2005, Vol 334, Num 1-3, pp 259-274, issn 0304-3975, 16 p.Article

Particle Swarm Optimization Based Reversible Circuit Synthesis Using Mixed Control Toffoli Gates : Selected Articles from the IEEE ISED 2012 ConferenceDATTA, Kamalika; SENGUPTA, Indranil; RAHAMAN, Hafizur et al.Journal of low power electronics (Print). 2013, Vol 9, Num 3, pp 363-372, issn 1546-1998, 10 p.Article

Synthesis and optimization of multiple-valued combinational and sequential reversible circuits with don't caresNIKNAFS, Aliakbar; MOHAMMADI, Majid.Integration (Amsterdam). 2013, Vol 46, Num 2, pp 189-196, issn 0167-9260, 8 p.Article

Debugging reversible circuitsWILLE, Robert; GROSSE, Daniel; FREHSE, Stefan et al.Integration (Amsterdam). 2011, Vol 44, Num 1, pp 51-61, issn 0167-9260, 11 p.Article

Multivalued and Reversible Logic Gates Implemented with Metallic Nanoparticles and Organic LigandsCERVERA, Javier; MAFE, Salvador.ChemPhysChem (Print). 2010, Vol 11, Num 8, pp 1654-1658, issn 1439-4235, 5 p.Article

A 12-transistor c-MOS building-block for reversible computersDE VOS, A.International journal of electronics. 1995, Vol 79, Num 2, pp 171-182, issn 0020-7217Article

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