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Power-aware computer systems (4th international workshop, PACS 2004, Portland OR, USA, December 5, 2004)Vijaykumar, T.N; Falsafi, Babak.Lecture notes in computer science. 2005, issn 0302-9743, isbn 3-540-29790-1, 1Vol, X-180 p, isbn 3-540-29790-1Conference Proceedings

Kilo-instruction ProcessorsCRISTAL, Adrian; ORTEGA, Daniel; LLOSA, Josep et al.Lecture notes in computer science. 2003, pp 10-25, issn 0302-9743, isbn 3-540-20359-1, 16 p.Conference Paper

Simultaneous Multithreading Trace ProcessorsWANG, K. F; ZHENZHOU JI; MINGZENG HU et al.Lecture notes in computer science. 2003, pp 96-103, issn 0302-9743, isbn 3-540-20054-1, 8 p.Conference Paper

Decisive aspects in the evolution of microprocessors. PrologSIMA, Dezsö; FALK, Howard.Proceedings of the IEEE. 2004, Vol 92, Num 12, issn 0018-9219, 1895,1896-1926 [32 p.]Article

Life is CMOS: Why chase the life after?SERY, George; BORKAR, Shekhar; DE, Vivek et al.Design automation conference. 2002, pp 78-83, isbn 1-58113-461-4, 6 p.Conference Paper

Trabecular bone microarchitecture : A reviewCHAPPARD, D; BASLE, M.-F; LEGRAND, E et al.Morphologie. 2008, Vol 92, Num 299, pp 162-170, issn 1286-0115, 9 p.Article

A single (Unified) shader GPU microarchitecture for embedded systemsMOYA, Victor; GONZALEZ, Carlos; ROCA, Jordi et al.Lecture notes in computer science. 2005, pp 286-301, issn 0302-9743, isbn 3-540-30317-0, 1Vol, 16 p.Conference Paper

Dynamic processor throttling for power efficient computationsKONDO, Masaaki; NAKAMURA, Hiroshi.Lecture notes in computer science. 2005, pp 120-134, issn 0302-9743, isbn 3-540-29790-1, 1Vol, 15 p.Conference Paper

An ontology for microarchitectural design knowledge : Postmodern software designGARZAS, Javier; PIATTINI, Mario.IEEE software. 2005, Vol 22, Num 2, pp 28-33, issn 0740-7459, 6 p.Article

Recovery Logics for Speculative Update Global and Local Branch HistoryJONG WOOK KWAK; CHU SHIK JHON.Lecture notes in computer science. 2006, pp 258-266, issn 0302-9743, isbn 3-540-47242-8, 1Vol, 9 p.Conference Paper

Low-overhead core swapping for thermal managementKURSUN, Eren; REINMAN, Glenn; SAIR, Suleyman et al.Lecture notes in computer science. 2005, pp 46-60, issn 0302-9743, isbn 3-540-29790-1, 1Vol, 15 p.Conference Paper

A comprehensive analysis of indirect branch predictionSANTANA, Oliverio J; FALCON, Ayose; FERNANDEZ, Enrique et al.Lecture notes in computer science. 2002, pp 133-145, issn 0302-9743, isbn 3-540-43674-X, 13 p.Conference Paper

Design tradeoffs for the Alpha EV8 conditional branch predictorSEZNEC, André; FELIX, Stephen; KRISHNAN, Venkata et al.Proceedings - International Symposium on Computer Architecture. 2002, pp 295-306, issn 1063-6897, isbn 0-7695-1605-X, 12 p.Conference Paper

Multi-core Demands Multi-InterfacesPATT, Yale N.ACM SIGPLAN Symposium on Principles & Practice of Parallel Programming. 2009, isbn 978-1-60558-397-6, 1Vol, p. 99Conference Paper

Microarchitectural characterization of JPEG-2000 softwareAOUADI, I; HAMMAMI, O.IWSSIP'02 : international workshop on systems, signals and image processing. 2002, pp 267-277, isbn 981-238-243-7, 11 p.Conference Paper

Accélération de la simulation modulaire = Modular simulation speed-upBOUACHE, Mourad; PARELLO, David; GOOSSENS, Bernard et al.TSI. Technique et science informatiques. 2011, Vol 30, Num 9, pp 1115-1134, issn 0752-4072, 20 p.Conference Paper

The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delaysHRISHIKESH, M. S; JOUPPI, Norman P; FARKAS, Keith I et al.Proceedings - International Symposium on Computer Architecture. 2002, pp 14-24, issn 1063-6897, isbn 0-7695-1605-X, 11 p.Conference Paper

Generalization of knowledge base in the expert system for microprogrammingSHIMIZU, T; SAKAMURA, K.Systems, computers, controls. 1984, Vol 15, Num 1, pp 20-29, issn 0096-8765Article

The impact of branch direction history combined with global branch history in branch predictionKWAK, Jong Wook; KIM, Ju-Hwan; JHON, Chu Shik et al.IEICE transactions on information and systems. 2005, Vol 88, Num 7, pp 1754-1758, issn 0916-8532, 5 p.Article

Context-independent codes for off-chip interconnectsMOHANRAM, Kartik; RIXNER, Scott.Lecture notes in computer science. 2005, pp 107-119, issn 0302-9743, isbn 3-540-29790-1, 1Vol, 13 p.Conference Paper

Scalable selective re-execution for EDGE architecturesDESIKAN, Rajagopalan; SETHUMADHAVAN, Simha; BURGER, Doug et al.ACM SIGPLAN notices. 2004, Vol 39, Num 11, pp 120-132, issn 1523-2867, 13 p.Conference Paper

Validating word-oriented processors for bit and Multi-word operationsLEE, Ruby B; XIAO YANG; SHI, Zhijie Jerry et al.Lecture notes in computer science. 2004, pp 473-488, issn 0302-9743, isbn 3-540-23003-3, 16 p.Conference Paper

Safe overprovisioning : Using power limits to increase aggregate throughputFEMAL, Mark E; FREEH, Vincent W.Lecture notes in computer science. 2005, pp 150-164, issn 0302-9743, isbn 3-540-29790-1, 1Vol, 15 p.Conference Paper

Accuracy Enhancement by Selective Use of Branch History in Embedded ProcessorJONG WOOK KWAK; SEONG TAE JHANG; CHU SHIK JHON et al.Lecture notes in computer science. 2006, pp 979-986, issn 0302-9743, isbn 3-540-34379-2, 8 p.Conference Paper

Effective dynamic voltage scaling through CPU-boundedness detectionHSU, Chung-Hsing; FENG, Wu-Chun.Lecture notes in computer science. 2005, pp 135-149, issn 0302-9743, isbn 3-540-29790-1, 1Vol, 15 p.Conference Paper

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