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Systolic counters with unique zero stateSTAN, Mircea R.IEEE International Symposium on Circuits and Systems. 2004, pp 909-912, isbn 0-7803-8251-X, 4 p.Conference Paper

Equivalence verification of polynomial datapaths with fixed-size bit-vectors using finite ring algebraSHEKHAR, Namrata; KALLA, Priyank; ENESCU, Florian et al.IEEE/ACM International Conference on Computer-Aided Design. 2005, pp 291-296, isbn 0-7803-9254-X, 1Vol, 6 p.Conference Paper

Modulo deflation in (2n +1, 2n, 2n -1) convertersSHAOQIANG BI; WEI WANG; AL-KHALILI, Asim et al.IEEE International Symposium on Circuits and Systems. 2004, pp 429-432, isbn 0-7803-8251-X, 4 p.Conference Paper

Estimating the Gowers Norm of Modulo Functions over Prime Fields : Foundations of Computer Science - Mathematical Foundations and Applications of Computer Science and AlgorithmsKAWACHI, Akinori; TANAKA, Hidetoki; WATANABE, Osamu et al.IEICE transactions on information and systems. 2012, Vol 95, Num 3, pp 755-762, issn 0916-8532, 8 p.Article

RNS multiplication/sum-of-squares unitsADAMIDIS, D; VERGES, H. T.IET computers & digital techniques (Print). 2007, Vol 1, Num 1, pp 38-48, issn 1751-8601, 11 p.Article

Efficient modulo 2n + 1 multipliers for diminished-1 representationCHEN, J. W; YAO, R. H.IET circuits, devices & systems (Print). 2010, Vol 4, Num 4, pp 291-300, issn 1751-858X, 10 p.Article

Generalized Combinatoric Accumulator : Information and Communication System SecurityDAE HYUN YUM; JAE WOO SEO; PIL JOONG LEE et al.IEICE transactions on information and systems. 2008, Vol 91, Num 5, pp 1489-1491, issn 0916-8532, 3 p.Article

An Efficient FPGA Design of Residue-to-Binary Converter for the Moduli Set {2n + 1, 2n, 2n - 1}GBOLAGADE, Kazeem Alagbe; VOICU, George Razvan; COTOFANA, Sorin Dan et al.IEEE transactions on very large scale integration (VLSI) systems. 2011, Vol 19, Num 8, pp 1500-1503, issn 1063-8210, 4 p.Article

Efficient Modulo 2n + 1 MultipliersJIAN WEN CHEN; RUO HE YAO; WEI JING WU et al.IEEE transactions on very large scale integration (VLSI) systems. 2011, Vol 19, Num 12, pp 2149-2158, issn 1063-8210, 10 p.Article

Area-time efficient end-around inverted carry addersVERGOS, H. T.Integration (Amsterdam). 2012, Vol 45, Num 4, pp 388-394, issn 0167-9260, 7 p.Article

Generalised fault-tolerant stored-unibit-transfer residue number system multiplier for moduli set {2n ― 1, 2n, 2n + 1}TIMARCHI, S; FAZLALI, M.IET computers & digital techniques (Print). 2012, Vol 6, Num 5, pp 269-276, issn 1751-8601, 8 p.Article

Improving residue number system multiplication with more balanced moduli sets and enhanced modular arithmetic structures : Design of circuits and integrated systemsCHAVES, R; SOUSA, L.IET computers & digital techniques (Print). 2007, Vol 1, Num 5, pp 472-480, issn 1751-8601, 9 p.Article

Efficient new approach for modulo 2n-1 addition in RNSPATEL, R. A; BENAISSA, M; BOUSSAKTA, S et al.IEE proceedings. Computers and digital techniques. 2006, Vol 153, Num 6, pp 399-405, issn 1350-2387, 7 p.Article

Diminished-1 modulo 2n+1 squarer designVERGES, H. T; EFSTATHIOU, C.IEE proceedings. Computers and digital techniques. 2005, Vol 152, Num 5, pp 561-566, issn 1350-2387, 6 p.Article

An SMT-Based Approach to Bounded Model Checking of Designs in State Transition Matrix : Formal ApproachKONG, Weiqiang; SHIRAISHI, Tomohiro; KATAHIRA, Noriyuki et al.IEICE transactions on information and systems. 2011, Vol 94, Num 5, pp 946-957, issn 0916-8532, 12 p.Article

Static Test Data Volume Reduction Using Complementation or Modulo-M AdditionPOMERANZ, Irith; REDDY, Sudhakar M.IEEE transactions on very large scale integration (VLSI) systems. 2011, Vol 19, Num 6, pp 1108-1112, issn 1063-8210, 5 p.Article

Design of efficient modulo 2n + 1 multipliersVERGOS, H. T; EFSTATHIOU, C.IET computers & digital techniques (Print). 2007, Vol 1, Num 1, pp 49-57, issn 1751-8601, 9 p.Article

Area-Time Efficient Modulo 2n -1 Adder Design Using Hybrid Carry SelectionLIN, Su-Hon; SHEU, Ming-Hwa.IEICE transactions on information and systems. 2008, Vol 91, Num 2, pp 361-362, issn 0916-8532, 2 p.Article

Space-time precoding for downlink transmission in multiple antenna CDMA systemsMOHAMMAD RAZAVIZADEH, S; KHANDANI, Amir K; VAHID TABATABA VAKILI et al.IEEE transactions on vehicular technology. 2007, Vol 56, Num 5, pp 2590-2602, issn 0018-9545, 13 p., 1Article

Efficient modulo 2n±1 squarersBAKALIS, D; VERGOS, H. T; SPYROU, A et al.Integration (Amsterdam). 2011, Vol 44, Num 3, pp 163-174, issn 0167-9260, 12 p.Article

A Novel Nonlinear Joint Transmitter-Receiver Processing Algorithm for the Downlink of Multiuser MIMO SystemsJIA LIU; KRZYMIEN, Witold A.IEEE transactions on vehicular technology. 2008, Vol 57, Num 4, pp 2189-2204, issn 0018-9545, 16 p.Article

Low complexity Reed-Solomon encoder using globally optimized finite field multipliersJITTAWUTIPOKA, J; NGARMNIL, J.Analog and digital techniques in electrical engineering. Conference. 2004, isbn 0-7803-8560-8, Vol4, 423-426Conference Paper

High-performance glitch-free digital frequency synthesiserCHAU, Y. A; CHEN, C.-F.Electronics Letters. 2008, Vol 44, Num 18, pp 1063-1065, issn 0013-5194, 3 p.Article

Robust Lossless Image Data Hiding Designed for Semi-Fragile Image AuthenticationZHICHENG NI; SHI, Yun Q; ANSARI, Nirwan et al.IEEE transactions on circuits and systems for video technology. 2008, Vol 18, Num 4, pp 497-509, issn 1051-8215, 13 p.Article

DPC-Based Hierarchical Broadcasting : Design and ImplementationBIN LIU; HONGXIANG LI; HUI LIU et al.IEEE transactions on vehicular technology. 2008, Vol 57, Num 6, pp 3895-3900, issn 0018-9545, 6 p.Article

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