An approach to sequential circuit construction in LSI programmable arraysPAPACHRISTOU, C. A; SARMA, D.IEE proceedings. Part E. Computers and digital techniques. 1983, Vol 130, Num 5, pp 159-164, issn 0143-7062Article

Design of reprogrammable FPLARAJSUMAN, R.Electronics Letters. 1989, Vol 25, Num 11, pp 715-716, issn 0013-5194, 2 p.Article

Function symmetries and decoded-PLA realizationEKTARE, A. B; AL-SHEAKHLY, M. K. H.Computers & electrical engineering. 1988, Vol 14, Num 3-4, pp 137-150, issn 0045-7906Article

A PLA microcontroller using horizontal firmwarePAPACHRISTOU, C. A.Microprocessing and microprogramming. 1984, Vol 14, Num 3-4, pp 223-230, issn 0165-6074Article

A new approach to the design of testable PLA'sREDDY, S. M; DONG SAM HA.IEEE transactions on computers. 1987, Vol 36, Num 2, pp 201-211, issn 0018-9340Article

A testable PLA design with low overhead and high fault coverageKHAKBAZ, J.IEEE transactions on computers. 1984, Vol 33, Num 8, pp 743-745, issn 0018-9340Article

Auto-test intégré de PLAs CMOS dynamiques = Built-in self test design for dynamic CMOS LAsIldevert, Michel; Cambon, Gaston.1992, 190 p.Thesis

Reprogrammable FPLA with universal test setRAJSUMAN, R; MALAIYA, Y. K; JAYASUMANA, A. P et al.IEE proceedings. Part E. Computers and digital techniques. 1990, Vol 137, Num 6, pp 437-441, issn 0143-7062Article

A new PLA design for universal testabilityFUJIWARA, H.IEEE transactions on computers. 1984, Vol 33, Num 8, pp 745-750, issn 0018-9340Article

Generation of a precise binary logarithm with difference grouping programmable logic arrayHAO-YUNG LO; AOKI, Y.IEEE transactions on computers. 1985, Vol 34, Num 8, pp 681-691, issn 0018-9340Article

Optical programmable cellular logic array for image processingLIREN LIU; XIAOBEN LIU; BO CUI et al.Applied optics. 1991, Vol 30, Num 8, pp 943-949, issn 0003-6935Article

Efficient algorithm for Weinberger array foldingSAIT, S. M; MUHAMMAD ABDUL-AZIZ AL-RASHED.International journal of electronics. 1990, Vol 69, Num 4, pp 509-518, issn 0020-7217Article

PLA logic minimization by simulated annealingYAO, X; LIU, C. L.Integration (Amsterdam). 1990, Vol 9, Num 3, pp 243-257, issn 0167-9260Article

Testable design of two-dimensional cellular logic arrays for detecting stuck-at and bridging faultsBIDYUT GUPTA; BHATTACHARYA, B. B; BASU, G. C et al.Computers & electrical engineering. 1988, Vol 14, Num 3-4, pp 65-74, issn 0045-7906Article

Realization of computers using programmable logic unitsYAMADA, H; NAKAMURA, T; SHIGEI, Y et al.Systems and computers in Japan. 1987, Vol 18, Num 8, pp 47-56, issn 0882-1666Article

Fault detection in programmable logic arraysSOMENZI, F; GAI, S.Proceedings of the IEEE. 1986, Vol 74, Num 5, pp 655-668, issn 0018-9219Article

An algorithm to derive the complement of a binary function with multiple-valued inputsSASAO, T.IEEE transactions on computers. 1985, Vol 34, Num 2, pp 131-140, issn 0018-9340Article

On chip testing of embedded p.l.a.sVARMA, P; AMBLER, A. P; BAKER, K et al.Journal of the Institution of Electronic and Radio Engineers. 1985, Vol 55, Num 9, pp 306-310, issn 0267-1689Article

Fault equivalence in PLAs and prevention designLIU, B.-D; SHAW, G.-T.Electronics Letters. 1990, Vol 26, Num 23, pp 1925-1926, issn 0013-5194Article

Three-step heuristic algorithm for optimal PLA column foldingYANG, Y.-Y; KYUNG, C.-M.Electronics Letters. 1988, Vol 24, Num 17, pp 1088-1090, issn 0013-5194Article

Built in test of folded PLAsFERNANDES, A. O; COURTOIS, B.Rapport de recherche - IMAG. 1988, issn 0750-7380, 23 p.Report

On the design of a redundant programmable logic array (RPLA)CHIN-LONG WEY; MAN-KUAN VAI; LOMBARDI, F et al.IEEE journal of solid-state circuits. 1987, Vol 22, Num 1, pp 114-117, issn 0018-9200Article

Field programmable gate arrays in spaceFERNANDEZ-LEON, Agustin.IEEE instrumentation & measurement magazine. 2003, Vol 6, Num 4, pp 42-48, issn 1094-6969, 7 p.Article

Tradeoff literals against support for logic synthesis of LUT-based FPGAsLU, A; DAGLESS, E; SAUL, J et al.IEE proceedings. Computers and digital techniques. 1996, Vol 143, Num 2, pp 111-119, issn 1350-2387Article

Absolute minimization of completely specified switching functionsSUNG JE HONG; MUROGA, S.IEEE transactions on computers. 1991, Vol 40, Num 1, pp 53-65, issn 0018-9340, 13 p.Article