Solutions Strategies for Die Shift Problem in Wafer Level Compression MoldingSHARMA, Gaurav; KUMAR, Aditya; RAO, Vempati Srinivas et al.IEEE transactions on components, packaging, and manufacturing technology (2011. Print). 2011, Vol 1, Num 3-4, pp 502-509, issn 2156-3950, 8 p.Article

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High Quality and Low Loss Millimeter Wave Passives Demonstrated to 77-GHz for SiP Technologies Using Embedded Wafer-Level Packaging Platform (EMWLP)YING YING LIM; XIANGHUA XIAO; SHIGUO LIU et al.IEEE transactions on advanced packaging. 2010, Vol 33, Num 4, pp 1061-1071, issn 1521-3323, 11 p.Article

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Wafer level package with thermal-stress-absorbing interface structure and elongated padKIM, Gu-Sung; SARAH EUNKYUNG LIM.Microelectronic engineering. 2012, Vol 89, pp 70-75, issn 0167-9317, 6 p.Conference Paper

Moldless encapsulation for LED wafer level packaging using integrated DRIE trenchesRONG ZHANG; RICKY LEE, S. W.Microelectronics and reliability. 2012, Vol 52, Num 5, pp 922-932, issn 0026-2714, 11 p.Article

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The WLP-FDTD Method for Periodic Structures With Oblique Incident WaveCAI, Zhao-Yang; BIN CHEN; QIN YIN et al.IEEE transactions on antennas and propagation. 2011, Vol 59, Num 10, pp 3780-3785, issn 0018-926X, 6 p.Article

Trends of power semiconductor wafer level packaging : Advances in wafer level packagingYONG LIU.Microelectronics and reliability. 2010, Vol 50, Num 4, pp 514-521, issn 0026-2714, 8 p.Article

Wafer-Level Glass Capping with Optical IntegrationHANSEN, U; MAUS, S; LEIB, J et al.Symposium on design, test, integration and packaging of MEMS/MOEMS. 2010, pp 237-241, isbn 978-2-35500-011-9, 1Vol, 5 p.Conference Paper

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Stress evolution during thermal cycling of copper/polyimide layered structuresCHUNSHENG ZHU; WENGUO NING; GAOWEI XU et al.Materials science in semiconductor processing. 2014, Vol 27, pp 819-826, issn 1369-8001, 8 p.Article

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Design and Process of 3D MEMS System-in-Package (SiP)LAU, John H.Journal of microelectronics and electronic packaging. 2010, Vol 7, Num 1, pp 10-15, issn 1551-4897, 6 p.Article

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