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Beyond MRAM, CMOS/MTJ Integration for Logic ComponentsPRENAT, Guillaume; DIENY, Bernard; WEI GUO et al.IEEE transactions on magnetics. 2009, Vol 45, Num 10, pp 3400-3405, issn 0018-9464, 6 p.Conference Paper

Performance Study of a Schottky Barrier Double-Gate MOSFET Using a Two-Dimensional Analytical ModelSCHWARZ, Mike; HOLTIJ, Thomas; KLOES, Alexander et al.I.E.E.E. transactions on electron devices. 2013, Vol 60, Num 2, pp 884-886, issn 0018-9383, 3 p.Article

N-Port T-Networks and Topologically Symmetric Circuit TheoryRAUTIO, James C.IEEE transactions on microwave theory and techniques. 2010, Vol 58, Num 4, pp 705-709, issn 0018-9480, 5 p.Article

Source-drain partitioning in MOSFETROY, Ananda S; ENZ, Christian C; SALLESE, Jean-Michel et al.I.E.E.E. transactions on electron devices. 2007, Vol 54, Num 6, pp 1384-1393, issn 0018-9383, 10 p.Article

Accurate Compact Modeling for Sub-20-nm NAND Flash Cell Array Simulation Using the PSP ModelJEON, Jongwook; IL HAN PARK; KANG, Myounggon et al.I.E.E.E. transactions on electron devices. 2012, Vol 59, Num 12, pp 3503-3509, issn 0018-9383, 7 p.Article

Implementation of Tunneling Phenomena in a CNTFET Compact ModelFREGONESE, Sébastien; MANEUX, Cristell; ZIMMER, Thomas et al.I.E.E.E. transactions on electron devices. 2009, Vol 56, Num 10, pp 2224-2231, issn 0018-9383, 8 p.Article

Computationally Efficient Physics-Based Compact CNTFET Model for Circuit DesignFREGONESE, Sébastien; CAZIN D'HONINCTHUN, Hugues; GOGUET, Johnny et al.I.E.E.E. transactions on electron devices. 2008, Vol 55, Num 6, pp 1317-1327, issn 0018-9383, 11 p.Article

Generic Carrier-Based Core Model for Undoped Four-Terminal Double-Gate MOSFETs Valid for Symmetric, Asymmetric, and Independent-Gate-Operation ModesFENG LIU; JIN HE; YUE FU et al.I.E.E.E. transactions on electron devices. 2008, Vol 55, Num 3, pp 816-826, issn 0018-9383, 11 p.Article

Physics-based compact model of nanoscale MOSFETs- : Part II: Effects of degeneracy on transportMUGNAINI, Giorgio; LANNACCONE, Giuseppe.I.E.E.E. transactions on electron devices. 2005, Vol 52, Num 8, pp 1802-1806, issn 0018-9383, 5 p.Article

BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate ControlKHANDELWAL, Sourabh; SINGH CHAUHAN, Yogesh; CALVIN HU, Chenming et al.I.E.E.E. transactions on electron devices. 2012, Vol 59, Num 8, pp 2019-2026, issn 0018-9383, 8 p.Article

Systematic Compact Modeling of Correlated Noise in Bipolar TransistorsHERRICHT, Jörg; SAKALAS, Paulius; RAMONAS, Mindaugas et al.IEEE transactions on microwave theory and techniques. 2012, Vol 60, Num 11, pp 3403-3412, issn 0018-9480, 10 p.Article

Compact modeling of thermal noise in the MOS transistorROY, A. S; ENZ, C. C.I.E.E.E. transactions on electron devices. 2005, Vol 52, Num 4, pp 611-614, issn 0018-9383, 4 p.Article

High-frequency circuit design oriented compact bipolar transistor modeling with HICUM : Analog circuit and device technologiesSCHROTER, Michael.IEICE transactions on electronics. 2005, Vol 88, Num 6, pp 1098-1113, issn 0916-8524, 16 p.Article

Electrical Modeling of Stochastic Spin Transfer Torque Writing in Magnetic Tunnel Junctions for Memory and Logic ApplicationsYUE ZHANG; WEISHENG ZHAO; PRENAT, Guillaume et al.IEEE transactions on magnetics. 2013, Vol 49, Num 7, pp 4375-4378, issn 0018-9464, 4 p.Conference Paper

Piecewise Linearization Technique for Compact Charge Modeling of Independent DG MOSFETJANDHYALA, Srivatsava; ABRAHAM, Aby; ANGHEL, Costin et al.I.E.E.E. transactions on electron devices. 2012, Vol 59, Num 7, pp 1974-1979, issn 0018-9383, 6 p.Article

An Efficient Robust Algorithm for the Surface-Potential Calculation of Independent DG MOSFETJANDHYALA, Srivatsava; MAHAPATRA, Santanu.I.E.E.E. transactions on electron devices. 2011, Vol 58, Num 6, pp 1663-1671, issn 0018-9383, 9 p.Article

Large-Signal Model for Independent DG MOSFETPANKAJ KUMAR THAKUR; MAHAPATRA, Santanu.I.E.E.E. transactions on electron devices. 2011, Vol 58, Num 1, pp 46-52, issn 0018-9383, 7 p.Article

A physics-based analytic solution to the MOSFET surface potential from accumulation to strong-inversion regionJIN HE; MANSUN CHAN; XING ZHANG et al.I.E.E.E. transactions on electron devices. 2006, Vol 53, Num 9, pp 2008-2016, issn 0018-9383, 9 p.Article

A unified compact model of electrical and thermal 3-D spreading resistance between eccentric rectangular and circular contactsKARMALKAR, Shreepad; VISHNU MOHAN, P; PRESENNA KUMAR, B et al.IEEE electron device letters. 2005, Vol 26, Num 12, pp 909-912, issn 0741-3106, 4 p.Article

Realization of multiple valued logic and memory by hybrid SETMOS architectureMAHAPATRA, Santanu; IONESCU, Adrian Mihai.IEEE transactions on nanotechnology. 2005, Vol 4, Num 6, pp 705-714, issn 1536-125X, 10 p.Article

A Compact Model for Dual-Gate One-Dimensional FET: Application to Carbon-Nanotube FETsFREGONESE, Sébastien; MANEUX, Cristell; ZIMMER, Thomas et al.I.E.E.E. transactions on electron devices. 2011, Vol 58, Num 1, pp 206-215, issn 0018-9383, 10 p.Article

Quantum Threshold Voltage Modeling of Short Channel Quad Gate Silicon Nanowire TransistorRAKESH KUMAR, P; MAHAPATRA, Santanu.IEEE transactions on nanotechnology. 2011, Vol 10, Num 1, pp 121-128, issn 1536-125X, 8 p.Article

Physics, Technology, and Modeling of Complementary Asymmetric MOSFETsBULUCEA, Constantin; BAHL, Sandeep R; FRENCH, William D et al.I.E.E.E. transactions on electron devices. 2010, Vol 57, Num 10, pp 2363-2380, issn 0018-9383, 18 p.Article

A PSP-Based Small-Signal MOSFET Model for Both Quasi-Static and Nonquasi-Static OperationsAARTS, Annemarie C. T; SMIT, Geert D. J; SCHOLTEN, Andries J et al.I.E.E.E. transactions on electron devices. 2008, Vol 55, Num 6, pp 1424-1432, issn 0018-9383, 9 p.Article

Modeling advanced FET technology in a compact modelDUNGA, Mohan V; LIN, Chung-Hsun; XUEMEI XI et al.I.E.E.E. transactions on electron devices. 2006, Vol 53, Num 9, pp 1971-1978, issn 0018-9383, 8 p.Article

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