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A family of compact genetic algorithms for intrinsic evolvable hardwareGALLAGHER, John C; VIGRAHAM, Saranyan; KRAMER, Gregory et al.IEEE transactions on evolutionary computation. 2004, Vol 8, Num 2, pp 111-126, issn 1089-778X, 16 p.Article

Highly Parallel FPGA Emulation for LDPC Error Floor Characterization in Perpendicular Magnetic Recording ChannelYU CAI; JEON, Seungjune; KEN MAI et al.IEEE transactions on magnetics. 2009, Vol 45, Num 10, pp 3761-3764, issn 0018-9464, 4 p.Conference Paper

Performance evaluation of partial response targets for perpendicular recording using field programmable gate arraysJEON, Seungjune; XINDE HU; LINGYAN SUN et al.IEEE transactions on magnetics. 2007, Vol 43, Num 6, pp 2259-2261, issn 0018-9464, 3 p.Conference Paper

Field-programmable gate-array-based investigation of the error floor of low-density parity check codes for magnetic recording channelsLINGYAN SUN; HONGWEI SONG; VIJAYA KUMAR, B. V. K et al.IEEE transactions on magnetics. 2005, Vol 41, Num 10, pp 2983-2985, issn 0018-9464, 3 p.Conference Paper

Full-Custom PCB Implementation of the FDTD/FIT Dedicated ComputerFUJITA, Yuya; KAWAGUCHI, Hideki.IEEE transactions on magnetics. 2009, Vol 45, Num 3, pp 1100-1103, issn 0018-9464, 4 p.Conference Paper

Cost-Efficient SHA Hardware AcceleratorsCHAVES, Ricardo; KUZMANOV, Georgi; SOUSA, Leonel et al.IEEE transactions on very large scale integration (VLSI) systems. 2008, Vol 16, Num 8, pp 999-1008, issn 1063-8210, 10 p.Article

Effective Uses of FPGAs for Brute-Force Attack on RC4 CiphersKWOK, Sammy H. M; LAM, Edmund Y.IEEE transactions on very large scale integration (VLSI) systems. 2008, Vol 16, Num 8, pp 1096-1100, issn 1063-8210, 5 p.Article

Concatenated Low-Density Parity-Check and BCH Coding System for Magnetic Recording Read Channel With 4 kB Sector FormatNINGDE XIE; WEI XU; TONG ZHANG et al.IEEE transactions on magnetics. 2008, Vol 44, Num 12, pp 4784-4789, issn 0018-9464, 6 p.Article

Hardware acceleration for finite-element electromagnetics : Efficient sparse matrix floating-point computations with FPGAsEL-KURDI, Yousef; GIANNACOPOULOS, Dennis; GROSS, Warren J et al.IEEE transactions on magnetics. 2007, Vol 43, Num 4, pp 1525-1528, issn 0018-9464, 4 p.Conference Paper

Radiation Hardened MRAM-Based FPGAGONCALVES, O; PRENAT, G; DIENY, B et al.IEEE transactions on magnetics. 2013, Vol 49, Num 7, pp 4355-4358, issn 0018-9464, 4 p.Conference Paper

An overview of power analysis attacks against field programmable gate arraysSTANDAERT, Francois-Xavier; PEETERS, Eric; ROUVROY, Gael et al.Proceedings of the IEEE. 2006, Vol 94, Num 2, pp 383-394, issn 0018-9219, 12 p.Article

Revisiting the Itoh-Tsujii Inversion Algorithm for FPGA PlatformsREBEIRO, Chester; SUJOY SINHA ROY; SANKARA REDDY, D et al.IEEE transactions on very large scale integration (VLSI) systems. 2011, Vol 19, Num 8, pp 1508-1512, issn 1063-8210, 5 p.Article

Application-dependent testing of FPGAsTAHOORI, Mehdi.IEEE transactions on very large scale integration (VLSI) systems. 2006, Vol 14, Num 9, pp 1024-1033, issn 1063-8210, 10 p.Article

Design and Implementation of a Fuzzy-Modified Ant Colony Hardware Structure for Image RetrievalKONSTANTINIDIS, Konstantinos; SIRAKOULIS, Georgios Ch; ANDREADIS, Ioannis et al.IEEE transactions on systems, man and cybernetics. Part C, Applications and reviews. 2009, Vol 39, Num 5, pp 520-533, issn 1094-6977, 14 p.Article

Evaluation of low-density parity-check codes on perpendicular magnetic recording modelXINDE HU; VIJAYA KUMAR, B. V. K.IEEE transactions on magnetics. 2007, Vol 43, Num 2, pp 727-732, issn 0018-9464, 6 p., 2Conference Paper

Hardwired MPEG-4 repetitive paddingKUZMANOV, Georgi; VASSILIADIS, Stamatis; VAN EIJNDHOVEN, Jos T. J et al.IEEE transactions on multimedia. 2005, Vol 7, Num 2, pp 261-268, issn 1520-9210, 8 p.Article

Internal and External Bitstream Relocation for Partial Dynamic ReconfigurationCORBETTA, Simone; MORANDI, Massimo; NOVATI, Marco et al.IEEE transactions on very large scale integration (VLSI) systems. 2009, Vol 17, Num 11, pp 1650-1654, issn 1063-8210, 5 p.Article

Design of flexible GF(2m) elliptic curve cryptography processorsBENAISSA, Mohammed; WEI MING LIM.IEEE transactions on very large scale integration (VLSI) systems. 2006, Vol 14, Num 6, pp 659-662, issn 1063-8210, 4 p.Article

Field-Programmable Gate Array Design of Implementing Simplex Growing Algorithm for Hyperspectral Endmember ExtractionCHANG, Chein-I; WEI XIONG; WU, Chao-Cheng et al.IEEE transactions on geoscience and remote sensing. 2013, Vol 51, Num 3, pp 1693-1700, issn 0196-2892, 8 p., 2Article

Exploration of Heterogeneous FPGAs for Mapping Linear Projection DesignsBOUGANIS, Christos-S; POUMARA, Iosifina; CHEUNG, Peter Y. K et al.IEEE transactions on very large scale integration (VLSI) systems. 2010, Vol 18, Num 3, pp 436-449, issn 1063-8210, 14 p.Article

Design-for-Manufacture for Multigate Oxide CMOS ProcessQI LIN; MEI MA; VO, Tony et al.IEEE transactions on semiconductor manufacturing. 2008, Vol 21, Num 1, pp 41-45, issn 0894-6507, 5 p.Conference Paper

Optimization of Pattern Matching Circuits for Regular Expression on FPGALIN, Cheng-Hung; HUANG, Chih-Tsun; JIANG, Chang-Ping et al.IEEE transactions on very large scale integration (VLSI) systems. 2007, Vol 15, Num 12, pp 1303-1310, issn 1063-8210, 8 p.Article

Secure Dual-Core Cryptoprocessor for Pairings Over Barreto-Naehrig Curves on FPGA PlatformGHOSH, Santosh; MUKHOPADHYAY, Debdeep; ROYCHOWDHURY, Dipanwita et al.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 3, pp 434-442, issn 1063-8210, 9 p.Article

Multi-FPGA System With Unlimited and Self-Timed Wave-Pipelined Multiplexed RoutingSTRAUCH, Tobias.IEEE transactions on very large scale integration (VLSI) systems. 2011, Vol 19, Num 9, pp 1549-1558, issn 1063-8210, 10 p.Article

A Special-Purpose Architecture for Solving the Breakpoint Median ProblemBAKOS, Jason D; ELENIS, Panormitis E.IEEE transactions on very large scale integration (VLSI) systems. 2008, Vol 16, Num 12, pp 1666-1676, issn 1063-8210, 11 p.Article

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