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ORION 2.0: A Power-Area Simulator for Interconnection NetworksKAHNG, Andrew B; BIN LI; PEH, Li-Shiuan et al.IEEE transactions on very large scale integration (VLSI) systems. 2012, Vol 20, Num 1, pp 191-196, issn 1063-8210, 6 p.Article

System-on-chip : Reuse and integrationSALEH, Resve; WILTON, Steve; MIRABBASI, Shahriar et al.Proceedings of the IEEE. 2006, Vol 94, Num 6, pp 1050-1069, issn 0018-9219, 20 p.Article

Mathematical Formalisms for Performance Evaluation of Networks-on-ChipABBAS ESLAMI KIASARI; JANTSCH, Axel; ZHONGHAI LU et al.ACM computing surveys. 2013, Vol 45, Num 3, issn 0360-0300, 38.1-38.41Article

AdNoC: Runtime Adaptive Network-on-Chip ArchitectureMOHAMMAD ABDULLAH AL FARUQUE; EBI, Thomas; HENKEL, Jörg et al.IEEE transactions on very large scale integration (VLSI) systems. 2012, Vol 20, Num 2, pp 257-269, issn 1063-8210, 13 p.Article

Throughput-Oriented NoC Topology Generation and Analysis for High Performance SoCsDUMITRIU, Victor; KHAN, Gul N.IEEE transactions on very large scale integration (VLSI) systems. 2009, Vol 17, Num 10, pp 1433-1446, issn 1063-8210, 14 p.Article

A Dedicated Monitoring Infrastructure for Multicore ProcessorsJIA ZHAO; MADDURI, Sailaja; VADLAMANI, Ramakrishna et al.IEEE transactions on very large scale integration (VLSI) systems. 2011, Vol 19, Num 6, pp 1011-1022, issn 1063-8210, 12 p.Article

It's a small world after all : NoC performance optimization via long-range link insertionOGRAS, Umit Y; MARCULESCU, Radu.IEEE transactions on very large scale integration (VLSI) systems. 2006, Vol 14, Num 7, pp 693-706, issn 1063-8210, 14 p.Conference Paper

Design and Implementation of Backtracking Wave-Pipeline Switch to Support Guaranteed Throughput in Network-on-ChipPHAM, Phi-Hung; PARK, Jongsun; MAU, Phuong et al.IEEE transactions on very large scale integration (VLSI) systems. 2012, Vol 20, Num 2, pp 270-283, issn 1063-8210, 14 p.Article

Robust Concurrent Online Testing of Network-on-Chip-Based SoCsBHOJWANI, Praveen S; MEMBER, Student; MAHAPATRA, Rabi N et al.IEEE transactions on very large scale integration (VLSI) systems. 2008, Vol 16, Num 9, pp 1199-1209, issn 1063-8210, 11 p.Article

A New Multiple-Round Dimension-Order Routing for Networks-on-ChipFU, Binzhang; HAN, Yinhe; LI, Huawei et al.IEICE transactions on information and systems. 2011, Vol 94, Num 4, pp 809-821, issn 0916-8532, 13 p.Article

Compiler-directed application mapping for NoC based chip multiprocessorsGUANGYU CHEN; FEIHUI LI; KANDEMIR, Mahmut et al.ACM SIGPLAN notices. 2007, Vol 42, Num 7, pp 155-157, issn 1523-2867, 3 p.Conference Paper

Design and Management of Voltage-Frequency Island Partitioned Networks-on-ChipOGRAS, Umit Y; MARCULESCU, Radu; MARCULESCU, Diana et al.IEEE transactions on very large scale integration (VLSI) systems. 2009, Vol 17, Num 3, pp 330-341, issn 1063-8210, 12 p.Conference Paper

3-D topologies for networks-on-chip : Systems-on-chipPAVLIDIS, Vasilis F; FRIEDMAN, Eby G.IEEE transactions on very large scale integration (VLSI) systems. 2007, Vol 15, Num 10, pp 1081-1090, issn 1063-8210, 10 p.Article

Mesh-of-Trees and Alternative Interconnection Networks for Single-Chip ParallelismBALKAN, Aydin O; GANG QU; VISHKIN, Uzi et al.IEEE transactions on very large scale integration (VLSI) systems. 2009, Vol 17, Num 10, pp 1419-1432, issn 1063-8210, 14 p.Article

A Low-Area Multi-Link Interconnect Architecture for GALS Chip MultiprocessorsZHIYI YU; BAAS, Bevan M.IEEE transactions on very large scale integration (VLSI) systems. 2010, Vol 18, Num 5, pp 750-762, issn 1063-8210, 13 p.Article

An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOSVANGAL, Sriram R; HOWARD, Jason; ERRAGUNTLA, Vasantha et al.IEEE journal of solid-state circuits. 2008, Vol 43, Num 1, pp 29-41, issn 0018-9200, 13 p.Conference Paper

Low-Power, High-Speed Transceivers for Network-on-Chip CommunicationSCHINKEL, Daniël; MENSINK, Eisse; KLUMPERINK, Eric A. M et al.IEEE transactions on very large scale integration (VLSI) systems. 2009, Vol 17, Num 1, pp 12-21, issn 1063-8210, 10 p.Article

A Case Study for NoC-Based Homogeneous MPSoC ArchitecturesTOTA, Sergio V; CASU, Mario R; RUO ROCH, Massimo et al.IEEE transactions on very large scale integration (VLSI) systems. 2009, Vol 17, Num 3, pp 384-388, issn 1063-8210, 5 p.Conference Paper

An Analytical Latency Model for Networks-on-ChipESLAMI KIASARI, Abbas; ZHONGHAI LU; JANTSCH, Axel et al.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 1, pp 113-123, issn 1063-8210, 11 p.Article

Application-Driven End-to-End Traffic Predictions for Low Power NoC DesignHUANG, Yoshi Shih-Chieh; CHOU, Kaven Chun-Kai; KING, Chung-Ta et al.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 2, pp 229-238, issn 1063-8210, 10 p.Article

An On-Chip Network Fabric Supporting Coarse-Grained Processor ArrayPHAM, Phi-Hung; MAU, Phuong; KIM, Jungmoon et al.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 1, pp 178-182, issn 1063-8210, 5 p.Article

An Energy and Performance Exploration of Network-on-Chip ArchitecturesBANERJEE, Amab; WOLKOTTE, Pascal T; MULLINS, Robert D et al.IEEE transactions on very large scale integration (VLSI) systems. 2009, Vol 17, Num 3, pp 319-329, issn 1063-8210, 11 p.Conference Paper

Practical Asynchronous Interconnect Network DesignQUINTON, Bradley R; GREENSTREET, Mark R; WILTON, Steven J. E et al.IEEE transactions on very large scale integration (VLSI) systems. 2008, Vol 16, Num 5, pp 579-588, issn 1063-8210, 10 p.Article

Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn GraphHOSSEINABADY, Mohammad; REZA KAKOEE, Mohammad; MATHEW, Jimson et al.IEEE transactions on very large scale integration (VLSI) systems. 2011, Vol 19, Num 8, pp 1469-1480, issn 1063-8210, 12 p.Article

Reconfigurable Routers for Low Power and High PerformanceMATOS, Débora; CONCATTO, Caroline; KREUTZ, Márcio et al.IEEE transactions on very large scale integration (VLSI) systems. 2011, Vol 19, Num 11, pp 2045-2057, issn 1063-8210, 13 p.Article

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