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Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniquesSAN MILLAN, Enrique; ENTRENA, Luis; ESPEJO, José Alberto et al.Journal of systems architecture. 2003, Vol 49, Num 12-15, pp 529-541, issn 1383-7621, 13 p.Article

Retiming DAG'sCALLAND, P. Y; MIGNOTTE, A; PEYRAN, O et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1998, Vol 17, Num 12, pp 1319-1325, issn 0278-0070Article

Revisiting cycle shrinking = Un nouveau regard sur la réduction de cycleRobert, Yves; Song, Siang W.1991, 19 p.Report

PROPRIETES DYNAMIQUES DES REGULATEURS AUTOMATIQUES D'AMPLIFICATION DISCRETSGRYAZNYKH IV.1976; RADIOTEKHNIKA; S.S.S.R.; DA. 1976; VOL. 31; NO 5; PP. 60-64; BIBL. 5 REF.Article

Scheduling of uniform multidimensional systems under resource constraintsPASSOS, N. L; SHA, E. H.-M.IEEE transactions on very large scale integration (VLSI) systems. 1998, Vol 6, Num 4, pp 719-730, issn 1063-8210Article

ILP-based cost-optimal DSP synthesis with module selection and data format conversionITO, K; LUCKE, L. E; PARHI, K. K et al.IEEE transactions on very large scale integration (VLSI) systems. 1998, Vol 6, Num 4, pp 582-594, issn 1063-8210Article

High-speed architectures for parallel long BCH encodersXINMIAO ZHANG; PARHI, Keshab K.IEEE transactions on very large scale integration (VLSI) systems. 2005, Vol 13, Num 7, pp 872-877, issn 1063-8210, 6 p.Article

Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scalingCHABINI, Noureddine; WOLF, Wayne.IEEE transactions on very large scale integration (VLSI) systems. 2004, Vol 12, Num 6, pp 573-589, issn 1063-8210, 17 p.Article

Wire retiming as fixpoint computationCHUAN LIN; HAI ZHOU.IEEE transactions on very large scale integration (VLSI) systems. 2005, Vol 13, Num 12, pp 1340-1348, issn 1063-8210, 9 p.Article

Efficient variable partitioning and scheduling for DSP processors with multiple memory modulesQINGFENG ZHUGE; EDWIN HSING-MEAN SHA; BIN XIAO et al.IEEE transactions on signal processing. 2004, Vol 52, Num 4, pp 1090-1099, issn 1053-587X, 10 p.Article

Design of Quantum-Dot Cellular Automata Circuits Using Cut-Set RetimingWEIQIANG LIU; LIANG LU; O'NEILL, Máire et al.IEEE transactions on nanotechnology. 2011, Vol 10, Num 5, pp 1150-1160, issn 1536-125X, 11 p.Article

Timing Jitter Reduction by All-Optical Signal Regeneration Using a Polarization Bistable VCSELMORI, Takashi; SATO, Yuuki; KAWAGUCHI, Hitoshi et al.Journal of lightwave technology. 2008, Vol 26, Num 13-16, pp 2946-2953, issn 0733-8724, 8 p.Article

Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraintsCHABINI, Noureddine; WOLF, Wayne.IEEE transactions on very large scale integration (VLSI) systems. 2005, Vol 13, Num 10, pp 1113-1126, issn 1063-8210, 14 p.Article

Characterization of All-Optical Regeneration Potentials of a Bistable Semiconductor Ring LaserBEI LI; MUHAMMAD IRFAN MEMON; MEZOSI, Gabor et al.Journal of lightwave technology. 2009, Vol 27, Num 17-20, pp 4233-4240, issn 0733-8724, 8 p.Article

Experimental Demonstration of Optical Retiming Using Temporal Soliton MoleculesJOHNSON, Stanley; PAU, Stanley; KÜPPERS, Franko et al.Journal of lightwave technology. 2011, Vol 29, Num 21-24, pp 3493-3499, issn 0733-8724, 7 p.Article

43 Gb/s decision circuits in InP DHBT technologyKRISHNAMURTHY, Karthikeyan; CHOW, Jimmy; MENSA, Dino et al.IEEE microwave and wireless components letters. 2004, Vol 14, Num 1, pp 28-30, issn 1531-1309, 3 p.Article

Railway crew rescheduling with retimingVEELENTURF, Lucas P; POTTHOFF, Daniel; HUISMAN, Dennis et al.Transportation research. Part C, Emerging technologies. 2012, Vol 20, Num 1, pp 95-110, issn 0968-090X, 16 p.Article

Exhaustive scheduling and retiming of digital signal processing systemsDENK, T. C; PARHI, K. K.IEEE transactions on circuits and systems. 2, Analog and digital signal processing. 1998, Vol 45, Num 7, pp 821-838, issn 1057-7130Article

Optimal clock period clustering for sequential circuits with retimingPEICHEN PAN; KARANDIKAR, A. K; LIU, C. L et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1998, Vol 17, Num 6, pp 489-498, issn 0278-0070Article

Retiming-based partial scanKAGARIS, D; TRAGOUDAS, S.IEEE transactions on computers. 1996, Vol 45, Num 1, pp 74-87, issn 0018-9340Article

Retiming control logicMAHESHWARI, N; SAPATNEKAR, S. S.Integration (Amsterdam). 1999, Vol 28, Num 1, pp 33-53, issn 0167-9260Article

Exploiting retiming in a guided simulation based validation methodologyGUPTA, A; ASHAR, P; MALIK, S et al.Lecture notes in computer science. 1999, pp 350-353, issn 0302-9743, isbn 3-540-66559-5Conference Paper

Computing the initial states of retimed circuitsTOUATI, H. J; BRAYTON, R. K.IEEE transactions on computer-aided design of integrated circuits and systems. 1993, Vol 12, Num 1, pp 157-162, issn 0278-0070Article

Energy-Efficient Retiming and Scheduling of Datapath-Dominant Digital SystemsNANDA, Rashmi; MARKOVIC, Dejan.Journal of low power electronics (Print). 2011, Vol 7, Num 3, pp 341-349, issn 1546-1998, 9 p.Article

Minimization of circuit registers : Retiming revisitedGAUJAL, Bruno; MAIRESSE, Jean.Discrete applied mathematics. 2008, Vol 156, Num 18, pp 3498-3505, issn 0166-218X, 8 p.Article

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