Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraintsCHABINI, Noureddine; WOLF, Wayne.IEEE transactions on very large scale integration (VLSI) systems. 2005, Vol 13, Num 10, pp 1113-1126, issn 1063-8210, 14 p.Article

Partitioning and gating technique for low-power multiplication in video processing applicationsNGO, Hau T; ASARI, Vijayan K.Microelectronics journal. 2009, Vol 40, Num 11, pp 1584-1591, issn 0959-8324, 8 p.Conference Paper

Analysis of dissipation energy of switching digital CMOS gates with coupled outputsMOLL, Francesc; ROCA, Miquel; ISERN, Eugeni et al.Microelectronics journal. 2003, Vol 34, Num 9, pp 833-842, issn 0959-8324, 10 p.Article

Wire Topology Optimization for Low Power CMOSZUBER, Paul; BAHLOUS, Othman; ILNSEHER, Thomas et al.IEEE transactions on very large scale integration (VLSI) systems. 2009, Vol 17, Num 1, pp 1-11, issn 1063-8210, 11 p.Article

A Binary Decision Diagram Structure for Probabilistic Switching Activity EstimationMACHADO, Felipe; TORROJA, Yago; RIESGO, Teresa et al.Journal of low power electronics (Print). 2008, Vol 4, Num 3, pp 247-262, issn 1546-1998, 16 p.Article

Diagnostic Test Sets with Increased Switching Activity for Transition FaultsPOMERANZ, Irith.Journal of low power electronics (Print). 2013, Vol 9, Num 1, pp 133-140, issn 1546-1998, 8 p.Conference Paper

A look-ahead synthesis technique with backtracking for switching activity reduction in low power high-level synthesisXIANWU XING; CHING CHUEN JONG.Microelectronics journal. 2007, Vol 38, Num 4-5, pp 595-605, issn 0959-8324, 11 p.Article

Reduced Power Transition Fault Test Sets for Circuits With Independent Scan Chain ModesPOMERANZ, Irith.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 7, pp 1354-1359, issn 1063-8210, 6 p.Article

BZ-FAD : ALow-Power Low-Area Multiplier Based on Shift-and-Add ArchitectureMOTTAGHI-DASTJERDI, M; AFZALI-KUSHA, A; PEDRAM, M et al.IEEE transactions on very large scale integration (VLSI) systems. 2009, Vol 17, Num 2, pp 302-306, issn 1063-8210, 5 p.Article

Transparent-Segmented-Scan without the Routing Overhead of Segmented-ScanPOMERANZ, Irith; REDDY, Sudhakar M.Journal of low power electronics (Print). 2011, Vol 7, Num 2, pp 245-253, issn 1546-1998, 9 p.Article

NCXplore: a design space exploration framework of temporal encoding for on-chip serial interconnectsKORNAROS, George.International journal of high performance systems architecture (Print). 2010, Vol 2, Num 3-4, pp 177-186, issn 1751-6528, 10 p.Article

Functional Broadside Tests with Minimum and Maximum Switching ActivityPOMERANZ, Irith; REDDY, Sudhakar M.Journal of low power electronics (Print). 2008, Vol 4, Num 3, pp 429-437, issn 1546-1998, 9 p.Article

A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan TestingYAMATO, Yuta; WEN, Xiaoqing; MIYASE, Kohei et al.IEICE transactions on information and systems. 2011, Vol 94, Num 4, pp 833-840, issn 0916-8532, 8 p.Article

Operation mode based high-level switching activity analysis for power estimation of digital circuitsSHIN, Hyunchul; LEE, Changhee.IEICE transactions on communications. 2007, Vol 90, Num 7, pp 1826-1834, issn 0916-8516, 9 p.Article

A low power test pattern generation for built-in self-test based circuitsBO YE; TIANWANG LI; QIAN ZHAO et al.International journal of electronics. 2011, Vol 98, Num 1-3, pp 301-309, issn 0020-7217, 9 p.Article

Statistical power supply dynamic noise prediction in hierarchical power grid and package networksGRAZIANO, M; PICCININI, G.Integration (Amsterdam). 2008, Vol 41, Num 4, pp 524-538, issn 0167-9260, 15 p.Article

A micropower low-voltage multiplier with reduced spurious switchingCHONG, Kwen-Siong; GWEE, Bah-Hwee; CHANG, Joseph S et al.IEEE transactions on very large scale integration (VLSI) systems. 2005, Vol 13, Num 2, pp 255-265, issn 1063-8210, 11 p.Article

Power minimization for dynamic PLAsTIEN, Tzyy-Kuen; TSAI, Chih-Shen; CHANG, Shih-Chieh et al.IEEE transactions on very large scale integration (VLSI) systems. 2006, Vol 14, Num 6, pp 616-624, issn 1063-8210, 9 p.Article

Embedded Transition Inversion Coding With Low Switching Activity for Serial LinksCHIU, Ching-Te; HUANG, Wen-Chih; LIN, Chih-Hsing et al.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 10, pp 1797-1810, issn 1063-8210, 14 p.Article

GlitchLess : Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch FilteringLAMOUREUX, Julien; LEMIEUX, Guy G. F; WILTON, Steven J. E et al.IEEE transactions on very large scale integration (VLSI) systems. 2008, Vol 16, Num 11, pp 1521-1534, issn 1063-8210, 14 p.Article

Test Strategies for Low-Power DevicesRAVIKUMAR, C. P; HIRECH, M; WEN, X et al.Journal of low power electronics (Print). 2008, Vol 4, Num 2, pp 127-138, issn 1546-1998, 12 p.Article

Power estimation techniques for FPGAsANDERSON, Jason H; NAJM, Farid N.IEEE transactions on very large scale integration (VLSI) systems. 2004, Vol 12, Num 10, pp 1015-1027, issn 1063-8210, 13 p.Conference Paper

Single Cycle Access Structure for Logic TestSTRAUCH, Tobias.IEEE transactions on very large scale integration (VLSI) systems. 2012, Vol 20, Num 5, pp 878-891, issn 1063-8210, 14 p.Article

Static-switching pulse domino: A switching-aware design technique for wide fan-in dynamic multiplexersSINGH, Rahul; HONG, Gi-Moon; KIM, Mino et al.Integration (Amsterdam). 2012, Vol 45, Num 3, pp 253-262, issn 0167-9260, 10 p.Conference Paper

Theoretical analysis of bus-invert codingLIN, Rung-Bin; TSAI, Chi-Ming.IEEE transactions on very large scale integration (VLSI) systems. 2002, Vol 10, Num 6, pp 929-935, issn 1063-8210, 7 p.Article