Low power electronics and designBARTON, Brock; PEDRAM, Massoud.IEEE transactions on very large scale integration (VLSI) systems. 1997, Vol 5, Num 4, pp 349-488, issn 1063-8210Conference Proceedings

Energy minimization using multiple supply voltagesCHANG, J.-M; PEDRAM, M.IEEE transactions on very large scale integration (VLSI) systems. 1997, Vol 5, Num 4, pp 436-443, issn 1063-8210Conference Paper

Embedded power supply for low-power DSPGUTNIK, V; CHANDRAKASAN, A. P.IEEE transactions on very large scale integration (VLSI) systems. 1997, Vol 5, Num 4, pp 425-435, issn 1063-8210Conference Paper

Entropic bounds on FSM switchingTYAGI, A.IEEE transactions on very large scale integration (VLSI) systems. 1997, Vol 5, Num 4, pp 456-464, issn 1063-8210Conference Paper

ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)MARCULESCU, Diana; HENKEL, Jörk.IEEE transactions on very large scale integration (VLSI) systems. 2008, Vol 16, Num 6, pp 609-682, issn 1063-8210, 73 p.Conference Paper

Robust RTL power macromodels : Special section on low-power electronics and designBOGLIOLO, A; BENINI, L.IEEE transactions on very large scale integration (VLSI) systems. 1998, Vol 6, Num 4, pp 578-581, issn 1063-8210Article

ISLPED'04 (proceedings of the 2004 International Symposium on Low Power Electronics and Design)International Symposium on Low Power Electronics and Design. 2004, isbn 1-58113-929-2, 1Vol, XIII-400 p, isbn 1-58113-929-2Conference Proceedings

Memory modeling for system synthesis : Special section on low-power electronics and designCOUMERI, S. L; THOMAS, D. E.IEEE transactions on very large scale integration (VLSI) systems. 2000, Vol 8, Num 3, pp 327-334, issn 1063-8210Article

International Symposium on Low Power Electronics and Design (ISLPED'00)IEEE transactions on very large scale integration (VLSI) systems. 2001, Vol 9, Num 1, pp 1-106, issn 1063-8210Conference Proceedings

Low-power encodings for global communication in CMOS VLSISTAN, M. R; BURLESON, W. P.IEEE transactions on very large scale integration (VLSI) systems. 1997, Vol 5, Num 4, pp 444-455, issn 1063-8210Conference Paper

Design considerations for high-frequency crystal oscillators digitally trimmable to sub-PPM accuracyHUANG, Q; BASEDAU, P.IEEE transactions on very large scale integration (VLSI) systems. 1997, Vol 5, Num 4, pp 408-416, issn 1063-8210Conference Paper

Instruction buffering to reduce power in processors for signal processingBAJWA, R. S; HIRAKI, M; KOJIMA, H et al.IEEE transactions on very large scale integration (VLSI) systems. 1997, Vol 5, Num 4, pp 417-424, issn 1063-8210Conference Paper

Exploring the design space of mixed swing quadrail for low-power digital circuitsKRISHNAMURTHY, R. K; CARLEY, L. R.IEEE transactions on very large scale integration (VLSI) systems. 1997, Vol 5, Num 4, pp 388-400, issn 1063-8210Conference Paper

Gate-level power and current simulation of CMOS integrated circuitsBOGLIOLO, A; BENINI, L; DE MICHELI, G et al.IEEE transactions on very large scale integration (VLSI) systems. 1997, Vol 5, Num 4, pp 473-488, issn 1063-8210Conference Paper

A programmable temperature monitoring device for tagging small fish : A prototype chip developmentFISCHER, G; DALY, J. C; RECKSIEK, C. W et al.IEEE transactions on very large scale integration (VLSI) systems. 1997, Vol 5, Num 4, pp 401-407, issn 1063-8210Conference Paper

Graded-channel MOSFET (GCMOSFET) for high performance, low voltage DSP applicationsMA, J; LIANG, H.-B; PRYOR, R. A et al.IEEE transactions on very large scale integration (VLSI) systems. 1997, Vol 5, Num 4, pp 352-359, issn 1063-8210Conference Paper

Gate sizing for constrained delay/power/area optimizationCOUDERT, O.IEEE transactions on very large scale integration (VLSI) systems. 1997, Vol 5, Num 4, pp 465-472, issn 1063-8210Conference Paper

Intrinsic MOSFET parameter fluctuations due to random dopant placementTANG, X; DE, V. K; MEINDL, J. D et al.IEEE transactions on very large scale integration (VLSI) systems. 1997, Vol 5, Num 4, pp 369-376, issn 1063-8210Conference Paper

The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuitsEISELE, M; BERTHOLD, J; SCHMITT-LANDSIEDEL, D et al.IEEE transactions on very large scale integration (VLSI) systems. 1997, Vol 5, Num 4, pp 360-368, issn 1063-8210Conference Paper

Theoretical bounds for switching activity analysis in finite-state machines : Special section on low-power electronics and designMARCULESCU, D; MARCULESCU, R; PEDRAM, M et al.IEEE transactions on very large scale integration (VLSI) systems. 2000, Vol 8, Num 3, pp 335-339, issn 1063-8210Article

Architectural optimization for low-power nonpipelined asynchronous systems : Special section on low power electronics and designPLANA, L. A; NOWICK, S. M.IEEE transactions on very large scale integration (VLSI) systems. 1998, Vol 6, Num 1, pp 56-65, issn 1063-8210Article

Statistical estimation of average power dissipation using nonparametric techniques : Special section on low power electronics and designYUAN, L.-P; TENG, C.-C; KANG, S.-M et al.IEEE transactions on very large scale integration (VLSI) systems. 1998, Vol 6, Num 1, pp 65-73, issn 1063-8210Article

Modeling and comparing CMOS implementations of the C-element : Special section on low-power electronics and designSHAMS, M; EBERGEN, J. C; ELMASRY, M. I et al.IEEE transactions on very large scale integration (VLSI) systems. 1998, Vol 6, Num 4, pp 563-567, issn 1063-8210Article

Vibration-to-electric energy conversionMENINGER, Scott; OSCAR MUR-MIRANDA, Jose; AMIRTHARAJAH, Rajeevan et al.IEEE transactions on very large scale integration (VLSI) systems. 2001, Vol 9, Num 1, pp 64-76, issn 1063-8210Conference Paper

Power management in high-level synthesis : Special section on low-power electronics and designLAKSHMINARAYANA, G; RAGHUNATHAN, A; JHA, N. K et al.IEEE transactions on very large scale integration (VLSI) systems. 1999, Vol 7, Num 1, pp 7-15, issn 1063-8210Article