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Results 1 to 25 of 23010

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ADPLL design parameters determinations through noise modelingBO JIANG; TIAN XIA.Integration (Amsterdam). 2015, Vol 48, pp 138-145, issn 0167-9260, 8 p.Article

Methodology for designing and verifying switched-capacitor sample and hold circuits used in data convertersMOHAMMED, Mahmood; KAWAR, Sanad; ABUGHARBIEH, Khaldoon et al.IET circuits, devices & systems (Print). 2014, Vol 8, Num 4, pp 252-262, issn 1751-858X, 11 p.Article

Current-Reused 2.4-GHz Direct-Modulation Transmitter With On-Chip Automatic TuningAMIR-ASLANZADEH, Hesam; PANKRATZ, Erik John; MISHRA, Chinmaya et al.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 4, pp 732-746, issn 1063-8210, 15 p.Article

A Bootstrapped Analog Switch with Constant On-Resistance : Analog CIrcuits and Related SoC Integration TechnologiesKIM, Sang-Hun; LEE, Yong-Hwan; CHUNG, Hoon-Ju et al.IEICE transactions on electronics. 2011, Vol 94, Num 6, pp 1069-1071, issn 0916-8524, 3 p.Article

A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth TrackingWENJING YIN; INTI, Rajesh; ELSHAZLY, Amr et al.IEEE journal of solid-state circuits. 2011, Vol 46, Num 8, pp 1870-1880, issn 0018-9200, 11 p.Conference Paper

A 300-800 MHz Tunable Filter and Linearized LNA Applied in a Low-Noise Harmonic-Rejection RF-Sampling ReceiverZHIYU RU; KLUMPERINK, Eric A. M; SAAVEDRA, Carlos E et al.IEEE journal of solid-state circuits. 2010, Vol 45, Num 5, pp 967-978, issn 0018-9200, 12 p.Conference Paper

Flexible baseband analog circuits for software-defined radio front-endsGIANNINI, Vito; CRANINCKX, Jan; D'AMICO, Stefano et al.IEEE journal of solid-state circuits. 2007, Vol 42, Num 7, pp 1501-1512, issn 0018-9200, 12 p.Conference Paper

Development of low-complexity all-digital frequency locked loop as 500 MHz reference clock generator for field-programmable gate arrayYUWONO, Sigit; HAN, Seok-Kyun; GIWAN YOON et al.IET circuits, devices & systems (Print). 2014, Vol 8, Num 2, pp 73-81, issn 1751-858X, 9 p.Article

Novel digitally programmable multiphase voltage controlled oscillator and its stability discussionJIE JIN; CHUNHUA WANG; JINGRU SUN et al.Microelectronics and reliability. 2014, Vol 54, Num 3, pp 595-600, issn 0026-2714, 6 p.Article

Jitter Analysis of Polyphase Filter-Based Multiphase Clock in Frequency MultiplierJEE KHOI YIN; CHAN, P. K.IEEE transactions on very large scale integration (VLSI) systems. 2012, Vol 20, Num 8, pp 1373-1382, issn 1063-8210, 10 p.Article

Increased Group-Delay Slope Loop System for Enhanced-Resolution Analog Signal ProcessingNIKFAL, Babak; GUPTA, Shulabh; CALOZ, Christophe et al.IEEE transactions on microwave theory and techniques. 2011, Vol 59, Num 6, pp 1622-1628, issn 0018-9480, 7 p.Article

Self-Dithered Digital Delta-Sigma Modulators for Fractional-N PLL : Analog CIrcuits and Related SoC Integration TechnologiesXU, Zule; GYU LEE, Jun; MASUI, Shoichi et al.IEICE transactions on electronics. 2011, Vol 94, Num 6, pp 1065-1068, issn 0916-8524, 4 p.Article

Nested Digital Background Calibration of a 12-bit Pipelined ADC Without an Input SHAHAOYUE WANG; XIAOYUE WANG; HURST, Paul J et al.IEEE journal of solid-state circuits. 2009, Vol 44, Num 10, pp 2780-2789, issn 0018-9200, 10 p.Article

Behavioral modeling, simulation and synthesis of multi-standard wireless receivers in MATLAB/SIMULINKMORGADO, A; RIVAS, V. J; DEL RIO, R et al.Integration (Amsterdam). 2008, Vol 41, Num 2, pp 269-280, issn 0167-9260, 12 p.Article

A 20 mW 3.24 mm2 Fully integrated GPS radio for location based servicesTORRE, Valentina Della; CONTA, Matteo; CHOKKALINGAM, Ramesh et al.IEEE journal of solid-state circuits. 2007, Vol 42, Num 3, pp 602-612, issn 0018-9200, 11 p.Article

A single-chip tri-band (2100, 1900, 850/800 MHz) WCDMA/HSDPA cellular transceiverKACZMAN, Daniel L; SHAH, Manish; SHEPHERD, Wayne P et al.IEEE journal of solid-state circuits. 2006, Vol 41, Num 5, pp 1122-1132, issn 0018-9200, 11 p.Conference Paper

A 2.5-3.125-Gb/s quad transceiver with second-order analog DLL-based CDRsCOBAN, Abdulkerim L; KOROGLU, Mustafa H; AHMED, Kashif A et al.IEEE journal of solid-state circuits. 2005, Vol 40, Num 9, pp 1940-1947, issn 0018-9200, 8 p.Conference Paper

A direct conversion receiver for the 3G WCDMA standardGHARPUREY, Ranjit; YANDURU, Naveen; DANTONI, Francesco et al.Custom integrated circuits conference. 2002, pp 239-242, isbn 0-7803-7250-6, 4 p.Conference Paper

A Range-Extended and Area-Efficient Time-to-Digital Converter Utilizing Ring-Tapped Delay LineWANG, Xin-Gang; WANG, Fei; JIA, Rui et al.IEICE transactions on electronics. 2013, Vol 96, Num 9, pp 1184-1194, issn 0916-8524, 11 p.Article

Design and Analysis of Dual-Mode Digital-Control Step-Up Switched-Capacitor Power Converter With Pulse-Skipping and Numerically Controlled Oscillator-Based Frequency ModulationKWAN, Hing-Kit; NG, David C. W; SO, Victor W. K et al.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 11, pp 2132-2140, issn 1063-8210, 9 p.Article

digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL ArchitectureNONIS, Roberto; GROLLITSCH, Werner; SANTA, Thomas et al.IEEE journal of solid-state circuits. 2013, Vol 48, Num 12, pp 3134-3145, issn 0018-9200, 12 p.Conference Paper

Zero-Crossing Detector Based Reconfigurable Analog SystemLAJEVARDI, Payam; CHANDRAKASAN, Anantha P; LEE, Hae-Seung et al.IEEE journal of solid-state circuits. 2011, Vol 46, Num 11, pp 2478-2487, issn 0018-9200, 10 p.Conference Paper

A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital ConverterTOKAIRIN, Takashi; OKADA, Mitsuji; KITSUNEZUKA, Masaki et al.IEEE journal of solid-state circuits. 2010, Vol 45, Num 12, pp 2582-2590, issn 0018-9200, 9 p.Conference Paper

Delayed feedback chaotic oscillator with improved spectral characteristicsTAMASEVICIUS, A; MYKOLAITIS, G; BUMELIENE, S et al.Electronics Letters. 2006, Vol 42, Num 13, pp 736-737, issn 0013-5194, 2 p.Article

A 3.5-GHz pll for fast low-IF/zero-IF LO switching in an 802.11 transceiverGIERKINK, Sander L. J; DANDAN LI; FRYE, Robert C et al.IEEE journal of solid-state circuits. 2005, Vol 40, Num 9, pp 1909-1921, issn 0018-9200, 13 p.Conference Paper

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