A ROM-less reverse RNS converter for moduli set {2^q± 1, 2^q ±3}JABERIPUR, Ghassem; AHMADIFAR, HamidReza.IET computers & digital techniques (Print). 2014, Vol 8, Num 1, pp 11-22, issn 1751-8601, 12 p.Article

Challenges and advances in Toffoli network optimisationDUECK, Gerhard W.IET computers & digital techniques (Print). 2014, Vol 8, Num 4, pp 172-177, issn 1751-8601, 6 p.Article

Power-aware floorplanning-based power through-silicon-via technology and bump minimisation for three-dimensional power delivery networkCHEOLJON JANG; JAEHWAN KIM; JONGWHA CHONG et al.IET computers & digital techniques (Print). 2014, Vol 8, Num 5, pp 210-218, issn 1751-8601, 9 p.Article

Sample preparation with multiple dilutions on digital microfluidic biochipsBHATTACHARJEE, Sukanta; BANERJEE, Ansuman; BHATTACHARYA, Bhargab B et al.IET computers & digital techniques (Print). 2014, Vol 8, Num 1, pp 49-58, issn 1751-8601, 10 p.Article

A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuitsMOHAMMAD HOSSEIN MOAIYERI; REZA FAGHIH MIRZAEE; DOOSTAREGAN, Akbar et al.IET computers & digital techniques (Print). 2013, Vol 7, Num 4, pp 167-181, issn 1751-8601, 15 p.Article

Static test compaction for mixed broadside and skewed-load transition fault test setsPOMERANZ, Irith.IET computers & digital techniques (Print). 2013, Vol 7, Num 1, pp 21-28, issn 1751-8601, 8 p.Article

HW/SW co-design of dedicated heterogeneous parallel systems: an extended design space exploration approachPOMANTE, Luigi.IET computers & digital techniques (Print). 2013, Vol 7, Num 6, pp 246-254, issn 1751-8601, 9 p.Article

Comments on 'Improving the speed of decimal division'LANG, T; NANNARELLI, A.IET computers & digital techniques (Print). 2012, Vol 6, Num 6, pp 370-371, issn 1751-8601, 2 p.Article

Customisation of on-chip network interconnects and experiments in field-programmable gate arraysHUR, J. Y; STEFANOV, T; WONG, S et al.IET computers & digital techniques (Print). 2012, Vol 6, Num 1, pp 59-68, issn 1751-8601, 10 p.Article

Functional broadside tests for embedded logic blocksPOMERANZ, I.IET computers & digital techniques (Print). 2012, Vol 6, Num 4, pp 223-231, issn 1751-8601, 9 p.Article

Multi-objective optimisations for a superscalar architecture with selective value predictionGELLERT, A; CALBOREAN, H; VINTAN, L et al.IET computers & digital techniques (Print). 2012, Vol 6, Num 4, pp 205-213, issn 1751-8601, 9 p.Article

Verification by parts: reusing component invariant checking resultsMITRA, S; GHOSH, P; DASGUPTA, P et al.IET computers & digital techniques (Print). 2012, Vol 6, Num 1, pp 19-32, issn 1751-8601, 14 p.Article

Decimal floating-point antilogarithmic converter based on selection by rounding: algorithm and architectureCHEN, D; HAN, L; KO, S.-B et al.IET computers & digital techniques (Print). 2012, Vol 6, Num 5, pp 277-289, issn 1751-8601, 13 p.Article

Application-specific topology generation algorithms for network-on-chip designTOSUN, S; AR, Y; OZDEMIR, S et al.IET computers & digital techniques (Print). 2012, Vol 6, Num 5, pp 318-333, issn 1751-8601, 16 p.Article

History-aware, resource-based dynamic scheduling for heterogeneous multi-core processorsJOOYA, A. Z; BANIASADI, A; ANALOUI, M et al.IET computers & digital techniques (Print). 2011, Vol 5, Num 4, pp 254-262, issn 1751-8601, 9 p.Article

Improving the speed of decimal divisionKAIVANI, A; HOSSEINY, A; JABERIPUR, G et al.IET computers & digital techniques (Print). 2011, Vol 5, Num 5, pp 393-404, issn 1751-8601, 12 p.Article

Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data localityMCKEOWN, S; WOODS, R.IET computers & digital techniques (Print). 2011, Vol 5, Num 2, pp 136-144, issn 1751-8601, 9 p.Article

Primary input cones based on test sequences in synchronous sequential circuitsPOMERANZ, I; REDDY, S. M.IET computers & digital techniques (Print). 2011, Vol 5, Num 1, pp 16-24, issn 1751-8601, 9 p.Article

Reconfigurable baseband processing architecture for communicationLU, W. Q; ZHAO, S; ZHOU, X. F et al.IET computers & digital techniques (Print). 2011, Vol 5, Num 1, pp 63-72, issn 1751-8601, 10 p.Article

Row-linear feedback shift register-column X-masking technique for simultaneous testing of many-core system chipsWANG, W.-C; HSU, C.-Y; LI, J et al.IET computers & digital techniques (Print). 2011, Vol 5, Num 4, pp 238-246, issn 1751-8601, 9 p.Article

Two-dimensional partially functional broadside testsPOMERANZ, I; REDDY, S. M.IET computers & digital techniques (Print). 2011, Vol 5, Num 4, pp 247-253, issn 1751-8601, 7 p.Article

Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integrationKARNIK, T; SOMASEKHAR, D; BORKAR, S et al.IET computers & digital techniques (Print). 2011, Vol 5, Num 3, pp 205-212, issn 1751-8601, 8 p.Article

Selected papers from the 10^th International Conference on Application of Concurrency to System Design (ACSD 2010)GOMEZ, Luís; KHOMENKO, Victor; FERNANDES, João et al.IET computers & digital techniques (Print). 2011, Vol 5, Num 6, issn 1751-8601, 69 p.Serial Issue

Indicating combinational logic decompositionTOMS, W. B; EDWARDS, D. A.IET computers & digital techniques (Print). 2011, Vol 5, Num 4, pp 331-341, issn 1751-8601, 11 p.Conference Paper

Design and implementation challenges for adoption of the IEEE 1500 standardHIGGINS, M; MACNAMEE, C; MULLANE, B et al.IET computers & digital techniques (Print). 2010, Vol 4, Num 1, pp 38-49, issn 1751-8601, 12 p.Article