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A 32-BIT VLSI CPU CHIPBEYERS JW; DOHSE LJ; FUCETOLA JP et al.1981; IEEE J. SOLID-STATE CIRCUITS; ISSN 0018-9200; USA; DA. 1981; VOL. 16; NO 5; PP. 537-542; BIBL. 3 REF.Article

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ELECTRON BEAM LITHOGRAPHY MOVING INTO FOCUSFUKATSU Y; SAKIYAMA T.1981; JEE, J. ELECTRON. ENG.; ISSN 0385-4507; JPN; DA. 1981; VOL. 18; NO 177; PP. 92-95; BIBL. 4 REF.Article

1.25 MU M DEEP-GROOVE-ISOLATED SELF-ALIGNED BIPOLAR CIRCUITSTANG DD; SOLOMON PM; NING TH et al.1982; IEEE JOURNAL OF SOLID-STATE CIRCUITS; ISSN 0018-9200; USA; DA. 1982; VOL. 17; NO 5; PP. 925-931; BIBL. 24 REF.Article

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PROCEDE IMPLANTE AUTOALIGNEDE BREBISSON M; TESSIER M.1980; ; FRA; DA. 1980; DGRST-77 7 0979; 25 P.: ILL.; 30 CM; BIBL. 3 REF.; ACTION CONCERTEE: COMPOSANTS ET CIRCUITS MICROMINIATURISESReport

FILM PROPERTIES OF MOSI₂ AND THEIR APPLICATION TO SELF-ALIGNED MOSI₂ GATE MOSFETMOCHIZUKI T; TSUJIMARU T; KASHIWAGI M et al.1980; IEEE J. SOLID-STATE CIRCUITS; ISSN 0018-9200; USA; DA. 1980; VOL. 15; NO 4; PP. 496-500; BIBL. 13 REF.Article

FULLY ION IMPLANTED DSA MOSIC.OHKURA I; OHMORI M; SHIMOTORI K et al.1977; JAP. J. APPL. PHYS.; JAP.; DA. 1977; VOL. 16; SUPPL. 1; PP. 167-171; BIBL. 11 REF.; (CONF. SOLID STATE DEVICES. 8. PROC.; TOKYO; 1976)Conference Paper

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SDX: a novel self-aligned technique and its application to high-speed bipolar LSÍsYAMAMOTO, Y; SAKUMA, K.I.E.E.E. transactions on electron devices. 1988, Vol 35, Num 10, pp 1601-1608, issn 0018-9383Article

SELF-ALIGNED TRANSISTOR WITH SIDEWALL BASE ELECTRODENAKAMURA T; MIYAZAKI T; TAKAHASHI S et al.1982; IEEE J. SOLID-STATE CIRCUITS; ISSN 0018-9200; USA; DA. 1982; VOL. 17; NO 2; PP. 226-230; BIBL. 10 REF.Article

MOS DEVICE FABRICATION USING X-RAY LITHOGRAPHYSUZUKI K; MATSUI J; ONO T et al.1981; J. ELECTROCHEM. SOC.; ISSN 0013-4651; USA; DA. 1981; VOL. 128; NO 11; PP. 2434-2437; BIBL. 11 REF.Article

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A NEW MOS INTEGRATED CIRCUIT FABRICATION USING SI₃N₄ FILM SELF-ALIGNMENT LIFTOFF TECHNIQUESYACHI T; YAMAUCHI N.1982; IEEE TRANS. ELECTRON. DEVICES; ISSN 0018-9383; USA; DA. 1982; VOL. 29; NO 2; PP. 243-247; BIBL. 11 REF.Article

A 3-NS 1-KBIT RAM USING SUPER SELF-ALIGNED PROCESS TECHNOLOGYSAKAI T; YAMAMOTO Y; KOBAYASHI Y et al.1981; IEEE J. SOLID-STATE CIRCUITS; ISSN 0018-9200; USA; DA. 1981; VOL. 16; NO 5; PP. 424-429; BIBL. 9 REF.Article

SUBNANOSECOND SELF-ALIGNED I²L/MTL CIRCUITSTANG DD; NING TH; ISAAC RD et al.1980; IEEE J. SOLID-STATE CIRCUITS; ISSN 0018-9200; USA; DA. 1980; VOL. 15; NO 4; PP. 444-449; BIBL. 22 REF.Article

A 400 PS BIPOLAR 18 BIT RALU USING ADVANCED PSASATO F; WAKAMATSU S; KUBOTA T et al.1980; IEEE J. SOLID-STATE CIRCUITS; ISSN 0018-9200; USA; DA. 1980; VOL. 15; NO 5; PP. 802-808; BIBL. 12 REF.Article

AN ADVANCED PSA TECHNOLOGY FOR HIGH-SPEED BIPOLAR LSINAKASHIBA H; ISHIDA I; AOMURA K et al.1980; IEEE J. SOLID-STATE CIRCUITS; ISSN 0018-9200; USA; DA. 1980; VOL. 15; NO 4; PP. 455-459; BIBL. 8 REF.Article

DSA MOS TRANSITOR AND ITS INTEGRATED CIRCUIT.HAYASHI Y; SEKIGAWA T; TARUI Y et al.1977; JAP. J. APPL. PHYS.; JAP.; DA. 1977; VOL. 16; SUPPL. 1; PP. 163-166; (CONF. SOLID STATE DEVICES. 8. PROC.; TOKYO; 1976)Conference Paper

Contribution à l'étude de la réalisation du transistor bipolaire à hétérojonction GaAlAs/GaAs à structure autoalignée en technologie double mesa = Optimization of a self-aligned double mesa technology for AlGaAs/GaAs heterojonction bipolar transistorsBimuala, Bamueni; L'Hoir, Alain.1991, 217 p.Thesis

A metallic system self-implemention during non-quasy-equilibrium relaxationBEKRENEV, A. N; BEZUGLOV, A. YU.Fizika i himiâ obrabotki materialov. 1995, Num 2, pp 122-127, issn 0015-3214Article

SELF-ALIGNING OPTICAL-FIBRE CONNECTOR WITH MAGNETIC-ALLOY-CLAD FIBRESANDO Y; NISHI I.1981; ELECTRON. LETT.; ISSN 0013-5194; GBR; DA. 1981; VOL. 17; NO 21; PP. 793-795; BIBL. 2 REF.Article

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