Domino inspired MOBILE networksNUNEZ, J; AVEDILLO, M. J; QUINTANA, J. M et al.Electronics letters. 2012, Vol 48, Num 5, pp 292-293, issn 0013-5194, 2 p.Article

Efficient realisation of MOS-NDR threshold logic gatesNUNEZ, J; AVEDILLO, M. J; QUINTANA, J. M et al.Electronics letters. 2009, Vol 45, Num 23, pp 1158-1161, issn 0013-5194, 4 p.Article

Relationship of soil characteristics to vegetation successions on a sequence of degraded and rehabilitated soils in HondurasPANIAGUA, A; KAMMERBAUER, J; AVEDILLO, M et al.Agriculture, ecosystems & environment. 1999, Vol 72, Num 3, pp 215-225, issn 0167-8809Article

Rentabilidad del uso de cubiertas de plástico en habichuela para control de saltahojas, Empoasca sp. problablemente kraemeri (Ross y Moore) = Rentabilité de l'utilisation de film plastique en culture de haricot pour lutter contre Empoasca kraemeri = Efficacy of use of plastic sheeting for control of Empoasca kraemeri in bean cropsANDREWS, K. L; VALVERDE, V. H; AVEDILLO, M et al.1985, Vol 26, Num 1, pp 140-148Article

Simplified single-phase clock scheme for MOBILE networksNUNEZ, J; AVEDILLO, M. J; QUINTANA, J. M et al.Electronics letters. 2011, Vol 47, Num 11, pp 648-650, issn 0013-5194, 3 p.Article

Single phase clock scheme for mobile logic gatesPETTENGHI, H; AVEDILLO, M. J; QUINTANA, J. M et al.Electronics Letters. 2006, Vol 42, Num 24, pp 1382-1383, issn 0013-5194, 2 p.Article

Transistor critical sizing in MOBILE followerQUINTANA, J. M; AVEDILLO, M. J.Electronics Letters. 2005, Vol 41, Num 10, pp 583-584, issn 0013-5194, 2 p.Article

Hazard-free edge-triggered D flipflop based on threshold gatesQUINTANA, J. M; AVEDILLO, M. J; RUEDA, A et al.Electronics Letters. 1994, Vol 30, Num 17, pp 1390-1391, issn 0013-5194Article

FSMTEST: synthesis for testability and test generation of PLA-based FSMAVEDILLO, M. J; QUINTANA, J. M; HUERTAS, J. L et al.IEE proceedings. Computers and digital techniques. 1994, Vol 141, Num 4, pp 221-228, issn 1350-2387Article

State merging and state splitting via state assignment: a new FSM synthesis algorithmAVEDILLO, M. J; QUINTANA, J. M; HUERTAS, J. L et al.IEE proceedings. Computers and digital techniques. 1994, Vol 141, Num 4, pp 229-237, issn 1350-2387Article

Area-optimised registers using a folded PLAHUERTAS, J. L; QUINTANA, J. M; AVEDILLO, M. J et al.IEE proceedings. Part G. Circuits devices and systems. 1990, Vol 137, Num 1, pp 28-32, issn 0956-3768Article

Efficient state reduction methods for PLA-based sequential circuitsAVEDILLO, M. J; QUINTANA, J. M; HUERTAS, J. L et al.IEE proceedings. Part E. Computers and digital techniques. 1992, Vol 139, Num 6, pp 491-500, issn 0143-7062Article