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GENERAL EXCITATION TABLE FOR A JK MULTISTABLE.ACHA JI; HUERTAS JL.1975; ELECTRON. LETTERS; G.B.; DA. 1975; VOL. 11; NO 25-26; PP. 624; BIBL. 8 REF.Article

EINE ZAEHLDEKADE MIT GETRIGGERTEN J-K-FLIP-FLOPS AUS D110C-BAUSTEINEN = COMPTEUR DECIMAL A BASCULES J-K REALISE AVEC DES COMPOSANTS DE LA SERIE D110CKUHNE H.1972; RADIO FERNSEHEN ELEKTRON.; DTSCH.; DA. 1972; VOL. 21; NO 24; PP. 814-815Serial Issue

APPLICATION EQUATIONS, TRANSITION EQUATIONS AND THE REALISATION OF SEQUENTIAL NETWORKS OF JK FLIP-FLOPS.PUCKNELL DA.1976; MONITOR; AUSTRAL.; DA. 1976; VOL. 37; NO 11; PP. 339-342; BIBL. 5 REF.Article

A FORMAL METHOD FOR DESIGNING SEQUENTIAL CIRCUITS FROM SYNCHRONOUS FLIP-FLOPS SUCH AS THE J-K TYPE USING A HYBRID SYNCHRONOUS-ASYNCHRONOUS TECHNIQUEDUNDERDALE H.1972; RADIO ELECTRON. ENGR; G.B.; DA. 1972; VOL. 42; NO 9; PP. 416-418Serial Issue

LOGISCHER ENTWURF SYNCHRONER ZAEHLSCHALTUNGEN MIT TTL-SCHALTKREISEN = CONCEPTION LOGIQUE DE CIRCUITS DE COMPTAGES SYNCHRONES AVEC CIRCUITS TTLWILL G.1973; RADIO FERNSEHEN ELEKTRON.; DTSCH.; DA. 1973; VOL. 22; NO 16; PP. 523-524Serial Issue

PARTICULARITES DU PROGRAMME D'ANALYSE DES PROCESSUS TRANSITOIRES DANS DES CIRCUITS INTEGRES A PLUSIEURS COMPOSANTSNORENKOV IP.1972; MIKROELEKTRONIKA; S.S.S.R.; DA. 1972; VOL. 1; NO 3; PP. 222-225; BIBL. 6 REF.Serial Issue

AN INTEGRATED JK FLIP-FLOP CIRCUIT.INABE Y; KATAOKA K.1977; I.E.E.E. J. SOLID-STATE CIRCUITS; U.S.A.; DA. 1977; VOL. 12; NO 4; PP. 403-406; BIBL. 2 REF.Article

Three-level m-sequence generation using ternary hybrid U-gate and J_RK_R flip-flop logic primitivesBLAKLEY, J. J; WEBB, J. A. C; LAVERTY, S. J et al.International journal of electronics. 1992, Vol 73, Num 3, pp 605-613, issn 0020-7217Article

CMOS J-K triflopSHALASH, S. A. H; AL-ZUBAIDY, M. A; RAHIM, J. A et al.International journal of electronics. 1985, Vol 58, Num 2, pp 355-363, issn 0020-7217Article

Energy-recovery flip-flop design using improved adiabatic pseudo-domino logic structureNG, K. W; NG, K. A; LAU, K. T et al.Microelectronics journal. 1999, Vol 30, Num 9, pp 851-854, issn 0959-8324Article

THE MANIPULATION AND LOGICAL IMPLEMENTATION OF COMPUTATION SCHEMATA FOR PARALLEL PROCESSES.HOWARD BV.sdIN: RESEAUX PETRI. JOURN. ETUD. RESEAUX PETRI; PARIS; 1977; PARIS; INST. PROGRAMMATION; DA. S.D.; PP. 115-135; ABS. FR.; BIBL. 18 REF.Conference Paper

THE J-K GATE.OBERMAN RMM.1976; I.E.E.E. TRANS. COMPUTERS; U.S.A.; DA. 1976; VOL. 25; NO 11; PP. 1156-1159; BIBL. 1 REF.Article

The concept of fuzzy flip-flopHIROTA, K; OZAWA, K.IEEE transactions on systems, man, and cybernetics. 1989, Vol 19, Num 5, pp 980-997, issn 0018-9472, 18 p.Article

Higher radix linear sequential circuit implementation via hybrid U and JK multiple-valued logic primitivesWEBB, J. A. C; LAVERTY, S. J; CAHILL, S. J et al.Electronics Letters. 1992, Vol 28, Num 3, pp 252-254, issn 0013-5194Article

N-MOS JK master/slave flip flop design for use in high speed control and counting applicationsASHOK SRIVASTAVA.Microelectronics and reliability. 1986, Vol 26, Num 2, pp 265-269, issn 0026-2714Article