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ECONOMICAL REALISATION OF ASYNCHRONOUS SEQUENTIAL CIRCUITS USING RANDOM-ACCESS MEMORIESTHOMAS B; CHANDRASEKHARAN PC.1981; IEE PROC., PART E; ISSN 0143-7062; GBR; DA. 1981; VOL. 128; NO 3; PP. 129-132; BIBL. 9 REF.Article

EIGENVECTOR ASSIGNMENT USING OUTPUT FEEDBACKSAMBANDAN A; CHANDRASEKHARAN PC.1981; INT. J. CONTROL; ISSN 0020-7179; GBR; DA. 1981; VOL. 34; NO 6; PP. 1143-1152; BIBL. 6 REF.Article

DESIGN OF OUTPUT FEEDBACK CONTROLLER WITH EIGENVALUE AND EIGENVECTOR INSENSITIVITY = SYNTHESE D'UN REGULATEUR A RETROACTION DE SORTIE AVEC INSENSIBILITE DES VALEURS PROPRES ET DES VECTEURS PROPRESSAMBANDAN A; CHANDRASEKHARAN PC.1981; INT. J. CONTROL; ISSN 0020-7179; GBR; DA. 1981; VOL. 33; NO 5; PP. 935-943; BIBL. 2 REF.Article

ECONOMICAL SYNTHESIS OF REGULAR EXPRESSIONS FOR LARGE-STATE SEQUENTIAL MACHINESBABU THOMAS; CHANDRASEKHARAN PC.1981; INT. J. ELECTRON. THEOR. EXP.; ISSN 0020-7217; GBR; DA. 1981; VOL. 51; NO 3; PP. 241-246; BIBL. 4 REF.Article

TEST SEQUENCE REDUCTION FOR LARGE. STATE SEQUENTIAL MACHINES THROUGH PARALLEL DECOMPOSITIONCHANDRASEKHARAN PC; THOMAS B.1981; Z. ELEKTR. INF.-ENERGIETECH.; ISSN 0323-4428; DDR; DA. 1981; VOL. 11; NO 4; PP. 349-358; BIBL. 11 REF.Article

LARGE STATE SEQUENTIAL MACHINE REALIZATION WITH MINIMUM ROM CAPACITYTHOMAS B; CHANDRASEKHARAN PC.1980; INT. J. ELECTRON. EXP.; ISSN 0020-7217; GBR; DA. 1980; VOL. 49; NO 1; PP. 29-38; BIBL. 3 REF.Article

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