Suppression of the floating-body effect in poly-Si thin-film transistors with self-aligned Schottky barrier source and ohmic body contact structureKUO, Po-Yi; CHAO, Tien-Sheng SR; LEI, Tan-Fu et al.IEEE electron device letters. 2004, Vol 25, Num 9, pp 634-636, issn 0741-3106, 3 p.Article

Temperature Dependence of Electron Mobility on Strained nMOSFETs Fabricated by Strain-Gate EngineeringCHANG, Tien-Shun; TSUNG YI LU; CHAO, Tien-Sheng et al.IEEE electron device letters. 2012, Vol 33, Num 7, pp 931-933, issn 0741-3106, 3 p.Article

Hydrogen Instability Induced by Postannealing on Poly-Si TFTsLIAO, Chia-Chun; LIN, Min-Chen; CHAO, Tien-Sheng et al.I.E.E.E. transactions on electron devices. 2012, Vol 59, Num 6, pp 1807-1809, issn 0018-9383, 3 p.Article

Characterization of Enhanced Stress Memorization Technique on nMOSFETs by Multiple Strain-Gate EngineeringLU, Tsung-Yi; CHANG, Tien-Shun; HUANG, Shih-An et al.I.E.E.E. transactions on electron devices. 2011, Vol 58, Num 4, pp 1023-1028, issn 0018-9383, 6 p.Article

Effects of Channel Width and Nitride Passivation Layer on Electrical Characteristics of Polysilicon Thin-Film TransistorsLIAO, Chia-Chun; LIN, Min-Chen; CHIANG, Tsung-Yu et al.I.E.E.E. transactions on electron devices. 2011, Vol 58, Num 11, pp 3812-3819, issn 0018-9383, 8 p.Article

High-performance poly-Si TFTs with fully Ni-self-aligned silicided S/D and gate structureKUO, Po-Yi; CHAO, Tien-Sheng; WANG, Ren-Jie et al.IEEE electron device letters. 2006, Vol 27, Num 4, pp 258-261, issn 0741-3106, 4 p.Article

A domain partition approach to parallel adaptive simulation of dynamic threshold voltage MOSFETYIMING LI; CHAO, Tien-Sheng; SZE, S. M et al.Computer physics communications. 2002, Vol 147, Num 1-2, pp 697-701, issn 0010-4655, 5 p.Conference Paper

Benefit of NMOS by Compressive SiN as Stress Memorization Technique and Its MechanismLIAO, Chia-Chun; CHIANG, Tsung-Yu; LIN, Min-Chen et al.IEEE electron device letters. 2010, Vol 31, Num 4, pp 281-283, issn 0741-3106, 3 p.Article

Poly-Si Thin-Film Transistor Nonvolatile Memory Using Ge Nanocrystals as a Charge Trapping Layer Deposited by the Low-Pressure Chemical Vapor DepositionKUO, Po-Yi; CHAO, Tien-Sheng; HUANG, Jyun-Siang et al.IEEE electron device letters. 2009, Vol 30, Num 3, pp 234-236, issn 0741-3106, 3 p.Article

Vertical n-Channel Poly-Si Thin-Film Transistors With Symmetric S/D Fabricated by Ni-Silicide-Induced Lateral-Crystallization TechnologyKUO, Po-Yi; CHAO, Tien-Sheng; LAI, Jiou-Teng et al.IEEE electron device letters. 2009, Vol 30, Num 3, pp 237-239, issn 0741-3106, 3 p.Article

Characteristics of self-aligned Si/Ge T-gate poly-Si thin-film transistors with high ON/OFF current ratioKUO, Po-Yi; CHAO, Tien-Sheng; HSIEH, Pei-Shan et al.I.E.E.E. transactions on electron devices. 2007, Vol 54, Num 5, pp 1171-1176, issn 0018-9383, 6 p.Article

The impact of deep Ni salicidation and NH₃ plasma treatment on nano-SOI FinFETsYOU, Hsin-Chiang; KUO, Po-Yi; KO, Fu-Hsiang et al.IEEE electron device letters. 2006, Vol 27, Num 10, pp 799-801, issn 0741-3106, 3 p.Article

A Novel p-n-Diode Structure of SONOS-Type TFT NVM With Embedded Silicon NanocrystalsCHIANG, Tsung-Yu; MA, William Cheng-Yu; WU, Yi-Hong et al.IEEE electron device letters. 2010, Vol 31, Num 11, pp 1239-1241, issn 0741-3106, 3 p.Article

Novel Symmetric Vertical-Channel Ni-Salicided Poly-Si Thin-Film Transistors With High ON/OFF-Current RatioWU, Yi-Hong; KUO, Po-Yi; LU, Yi-Hsien et al.IEEE electron device letters. 2010, Vol 31, Num 11, pp 1233-1235, issn 0741-3106, 3 p.Article

High-Performance Metal-Induced Laterally Crystallized Polycrystalline Silicon P-Channel Thin-Film Transistor With TaN/HfO₂ Gate Stack StructureMA, Ming-Wen; CHAO, Tien-Sheng; SU, Chun-Jung et al.IEEE electron device letters. 2008, Vol 29, Num 6, pp 592-594, issn 0741-3106, 3 p.Article

Enhancement of Open-Circuit Voltage Using CF₄ Plasma Treatment on Nitric Acid OxidesLIN, Je-Wei; WU, Chien-Hung; WU, Sheng-Wei et al.IEEE electron device letters. 2013, Vol 34, Num 5, pp 665-667, issn 0741-3106, 3 p.Article

Low-Temperature Polycrystalline-Silicon Tunneling Thin-Film Transistors With MILCCHEN, Yi-Hsuan; YEN, Li-Chen; CHANG, Tien-Shun et al.IEEE electron device letters. 2013, Vol 34, Num 8, pp 1017-1019, issn 0741-3106, 3 p.Article

Susceptor Coupling for the Uniformity and Dopant Activation Efficiency in Implanted Si Under Fixed-Frequency Microwave AnnealLEE, Yao-Jen; HSUEH, Fu-Kuo; CURRENT, Michael I et al.IEEE electron device letters. 2012, Vol 33, Num 2, pp 248-250, issn 0741-3106, 3 p.Article

Low-temperature polycrystalline silicon thin-film flash memory with hafnium silicateLIN, Yu-Hsien; CHIEN, Chao-Hsin; CHOU, Tung-Huan et al.I.E.E.E. transactions on electron devices. 2007, Vol 54, Num 3, pp 531-536, issn 0018-9383, 6 p.Article

High-Performance Double-Layer Nickel Nanocrystal Memory by Ion Bombardment TechniqueLIU, Sheng-Hsien; YANG, Wen-Luh; LIN, Yu-Hsien et al.I.E.E.E. transactions on electron devices. 2013, Vol 60, Num 10, pp 3393-3399, issn 0018-9383, 7 p.Article

Improved Rear-Side Passivation by Atomic Layer Deposition Al₂O₃/SiN_x Stack Layers for High V_OC Industrial p-Type Silicon Solar CellsLIN, Je-Wei; CHEN, Yi-Yang; GAN, Jon-Yiew et al.IEEE electron device letters. 2013, Vol 34, Num 9, pp 1163-1165, issn 0741-3106, 3 p.Article

Channel Film Thickness Effect of Low-Temperature Polycrystalline-Silicon Thin-Film TransistorsCHENG-YU MA, William; CHIANG, Tsung-Yu; YEH, Chi-Ruei et al.I.E.E.E. transactions on electron devices. 2011, Vol 58, Num 4, pp 1268-1272, issn 0018-9383, 5 p.Article

CoTiO₃ high-κ dielectrics on HSG for DRAM applicationsCHAO, Tien-Sheng; KU, Wei-Ming; LIN, Hong-Chin et al.I.E.E.E. transactions on electron devices. 2004, Vol 51, Num 12, pp 2200-2204, issn 0018-9383, 5 p.Article

Physical Mechanism of High-Programming-Efficiency Dynamic-Threshold Source-Side Injection in Wrapped-Select-Gate SONOS for NOR-Type Flash MemoryWANG, Kuan-Ti; CHAO, Tien-Sheng; HSIEH, Tsung-Min et al.IEEE electron device letters. 2009, Vol 30, Num 11, pp 1206-1208, issn 0741-3106, 3 p.Article

Impacts of Fluorine Ion Implantation With Low-Temperature Solid-Phase Crystallized Activation on High-κ LTPS-TFTMA, Ming-Wen; CHEN, Chih-Yang; SU, Chun-Jung et al.IEEE electron device letters. 2008, Vol 29, Num 2, pp 168-170, issn 0741-3106, 3 p.Article