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au.\*:("CHAPPELL SG")

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LOGIC ANALYZER FOR MAINTENANCE PLANNING: AUTOMATIC TEST GENERATION FOR ASYNCHRONOUS DIGITAL CIRCUITS. = ANALYSEUR DE CIRCUITS LOGIQUES POUR LA PLANIFICATION DE LA MAINTENANCE: CREATION AUTOMATIQUE DE TESTS DE CIRCUITS NUMERIQUES ASYNCHRONESCHAPPELL SG.1974; BELL SYST. TECH. J.; U.S.A.; DA. 1974; VOL. 53; NO 8; PP. 1477-1503; BIBL. 9 REF.Article

DEDUCTIVE FAULT SIMULATION WITH FUNCTIONAL BLOCKS = SIMULATION DEDUCTIVE DE FAUTES AVEC DES BLOCS FONCTIONNELSMENON PR; CHAPPELL SG.1978; I.E.E.E. TRANS. COMPUTERS; USA; DA. 1978; VOL. 27; NO 8; PP. 689-695; BIBL. 15 REF.Article

LOGIC ANALYZER FOR MAINTENANCE PLANNING: LOGIC-CIRCUIT SIMULATORS. = ANALYSEUR DE CIRCUITS LOGIQUES POUR LA PLANIFICATION DE MAINTENANCE: PROGRAMMES DE SIMULATIONCHAPPELL SG; ELMENDORF CH; SCHMIDT LD et al.1974; BELL SYST. TECH. J.; U.S.A.; DA. 1974; VOL. 53; NO 8; PP. 1451-1476; BIBL. 14 REF.Article

COMPARAISON OF PARALLEL AND DEDUCTIVE FAULT SIMULATION METHODS.YU PANG CHANG H; CHAPPELL SG; ELMENDORF CH et al.1974; I.E.E.E. TRANS. COMPUTERS; U.S.A.; DA. 1974; VOL. 23; NO 11; PP. 1132-1138; BIBL. 8 REF.Article

EPLX: A HIGH LEVEL LANGUAGE FOR ELECTRONIC SWITCHING SYSTEMSCHAPPELL SG; JESSOP WH; GUTTMAN N et al.1978; COMPSAC 78. INTERNATIONAL COMPUTER SOFTWARE APPLICATIONS CONFERENCE. 2/1978-11-13/CHICAGO; USA; NEW YORK: IEEE; DA. 1978; PP. 78-83; BIBL. 11 REF.Conference Paper

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