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I2LII.COOK B; MCNALLY SH; AUNG SAN et al.1975; IN: INT. ELECTRON DEVICES MEET.; WASHINGTON, D.C.; 1975; NEW YORK; INST. ELECTR. ELECTRON. ENG.; DA. 1975; PP. 284-287; BIBL. 4 REF.; ART. ANGL.Conference Paper

FIELD PROGRAMMABLE LOGIC DEVICESLARSON TL; DOWNEY C.1980; ELECTRON. ENG.; ISSN 0013-4902; GBR; DA. 1980; VOL. 52; NO 633; PP. 37-54; (10 P.); BIBL. 7 REF.Article

VERTICAL INJECTION LOGIC.NAKANO T; HORIBA Y; YASUOKA A et al.1975; IN: INT. ELECTRON DEVICES MEET.; WASHINGTON, D.C.; 1975; NEW YORK; INST. ELECTR. ELECTRON. ENG.; DA. 1975; PP. 555-558; BIBL. 4 REF.Conference Paper

FABRICATION AND PERFORMANCE OF CON IMPLANTED I2L DEVICES.HANSON JW; FORDEWALT JN; HUBER RJ et al.1975; IN: INT. ELECTRON DEVICES MEET.; WASHINGTON, D.C.; 1975; NEW YORK; INST. ELECTR. ELECTRON. ENG.; DA. 1975; PP. 281-283; BIBL. 3 REF.Conference Paper

PLAS ZUR LOESUNG VON VERTEILUNGSAUFGABEN. = LES RESEAUX LOGIQUES PROGRAMMABLES POUR LA RESOLUTION DES PROBLEMES DE REPARTITIONEICHHOFER H; TIMM V.1977; ELEKTRONIK; DTSCH.; DA. 1977; VOL. 26; NO 6; PP. 59-76 (6P.); BIBL. 8 REF.Article

DESIGN OF LARGE ALUS USING MULTIPLE PLA MACROSSCHMOOKLER MS.1980; I.B.M. J. RES. DEVELOP.; USA; DA. 1980; VOL. 24; NO 1; PP. 2-14; BIBL. 6 REF.Article

OPTIMALISATION DES FONCTIONS BOOLEENNES ET UTILISATION DE RESEAUX LOGIQUES PROGRAMMESMONCHAUD S; LEMAIRE B; CHEN CHIN HUA et al.1978; NOUV. AUTOMATISME; FRA; DA. 1978; VOL. 23; NO 9-10; PP. 273-276Article

UNIVERSAL LOGIC GATE AND ITS APPLICATIONS.MURUGESAN S.1977; INTERNATION. J. ELECTRON.; G.B.; DA. 1977; VOL. 42; NO 1; PP. 55-63; BIBL. 7 REF.Article

HIGH SPEED CURRENT MODE LOGIC FOR LSICOOPERMAN M.1980; I.E.E.E. TRANS. CIRCUITS SYST.; USA; DA. 1980; VOL. 27; NO 7; PP. 626-635; BIBL. 8 REF.Article

A HEURISTIC TEST-PATTERN GENERATOR FOR PROGRAMMABLE LOGIC ARRAYSEICHELBERGER EB; LINDBLOOM E.1980; I.B.M. J. RES. DEVELOP.; USA; DA. 1980; VOL. 24; NO 1; PP. 15-23; BIBL. 10 REF.Article

SCHALTUNGSENTWURF MIT ULA-BAUSTEINEN. ERFAHRUNGEN, KOSTENVERGLEICH, ANWENDUNGEN. = LES PROJETS DE CIRCUITS UTILISANT LES COMPOSANTS ULA. RESULTATS, PRIX, APPLICATIONSRYMUS J.1977; ELEKTRONIK; DTSCH.; DA. 1977; VOL. 26; NO 6; PP. 79-84; BIBL. 2 REF.Article

AMELIORATION DE LA VITESSE ET DES POSSIBILITES D'APPLICATION DE LA LOGIQUE A INJECTION AUX CIRCUITS COMPLEXES.GUETIN P; KAIRE JC.1976; DGRST-7470402; FR.; DA. 1976; PP. 1-23; BIBL. 3 REF.; (RAPP. FINAL, ACTION CONCERTEE: CCM)Report

ON THE IMPACT OF HDLC ZERO INSERTION AND DELETION ON LINK UTILIZATION AND RELIABILITYMA JS.1982; IEEE TRANS. COMMUN.; ISSN 0090-6778; USA; DA. 1982; VOL. 30; NO 2; PP. 375-381; BIBL. 4 REF.Article

METHODE DE CONCEPTION DES SYSTEMES LOGIQUES: LE TABLEAU DES PRODUITSAUMIAUX M.1982; MINIS ET MICROS; ISSN 0336-4585; FRA; DA. 1982; VOL. 7; NO 158; PP. 47-50Article

PLAS OR MPS. AT TIMES THEY COMPETE, AND AT OTHER TIMES THEY COOPERATE.1976; ELECTRON. DESIGN; U.S.A.; DA. 1976; VOL. 24; NO 18; PP. 24-30 (4P.)Article

A DESIGN OF PROGRAMMABLE LOGIC ARRAYS WITH UNIVERSAL TESTSFUJIWARA H; KINOSHITA K.1981; IEEE TRANS. CIRCUITS SYST.; ISSN 0098-4094; USA; DA. 1981; VOL. 28; NO 11; PP. 1027-1032; BIBL. 12 REF.Article

STRUCTURES HOMOGENES SPECIALISEES UTILISEES COMME MATRICES LOGIQUES PROGRAMMABLESFET YA I.1979; AVTOMAT. VYCHISLIT. TEKH.; SUN; DA. 1979; NO 6; PP. 67-72; BIBL. 11 REF.Article

ANALYZE I2L ACCURATELY.COOK B.1977; ELECTRON. DESIGN; U.S.A.; DA. 1977; VOL. 25; NO 13; PP. 90-92Article

AN ASSOCIATIVE LOGIC MATRIX.GREER DL.1976; I.E.E.E. J. SOLID. STATE CIRCUITS; U.S.A.; DA. 1976; VOL. 11; NO 5; PP. 679-691; BIBL. 14 REF.Article

METHODE DE CONSTRUCTION D'UN TEST DE CONTROLE POUR MATRICES LOGIQUES PROGRAMMABLESVOLYNSKIJ MB; NOVOSELOV VG.1983; MIKROELEKTRONIKA; ISSN 0544-1269; SUN; DA. 1983; VOL. 12; NO 1; PP. 55-64; BIBL. 8 REF.Article

FIELD-PROGRAMMABLE ARRAYS: POWERFUL ALTERNATIVES TO RANDOM LOGICCAVLAN N; DURHAM SJ.1979; ELECTRONICS; USA; DA. 1979; VOL. 52; NO 14; PP. 109-114Article

MODIFIED PROGRAMMABLE LOGIC ARRAY WITH MORE PRODUCT TERMS.BENNETT LAM.1977; ELECTRON. LETTERS; G.B.; DA. 1977; VOL. 13; NO 15; PP. 443-445; BIBL. 1 REF.Article

STABILISATION DES NIVEAUX LOGIQUES ET DES SEUILS DE COMMUTATION DES CIRCUITS A FAIBLES SIGNAUX DE LA LOGIQUE A LIAISON D'EMETTEURIVANOV YU P; SHAGURIN II.1981; IZV. VYSS. UCEBN. ZAVED., RADIOELEKTRON.; ISSN 0021-3470; SUN; DA. 1981; VOL. 24; NO 7; PP. 34-38; BIBL. 11 REF.Article

DESIGN AUTOMATION AND THE PROGRAMMABLE LOGIC ARRAY MACROGOLDEN RL; LATUS PA; LOWY P et al.1980; I.B.M. J. RES. DEVELOP.; USA; DA. 1980; VOL. 24; NO 1; PP. 23-31; BIBL. 9 REF.Article

PLAS ENHANCE DIGITAL PROCESSOR SPEED AND CUT COMPONENT COUNT.REYLING G.1974; ELECTRONICS; U.S.A.; DA. 1974; VOL. 47; NO 16; PP. 109-114Article

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