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Logic networks with a minimum number of NOR(NAND) gates for parity functions of n variablesHUNG CHI LAI; MUROGA, S.IEEE transactions on computers. 1987, Vol 36, Num 2, pp 157-166, issn 0018-9340Article

HEURISTIC UNLOADING PROCEDURE FOR NAND AND NOR GATESDUBUS D; TOSSER A.1978; INTERNATION. J. ELECTRON.; GBR; DA. 1978; VOL. 45; NO 2; PP. 147-159; BIBL. 5 REF.Article

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SYNTHESIS OF A HAZARDLESS NAND NETWORK.AGUSA K; KAMBAYASHI Y.1975; SYST. COMPUTERS CONTROLS; U.S.A.; DA. 1975; VOL. 6; NO 2; PP. 13-21; BIBL. 12 REF.Article

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INJECTED VOLTAGE LOW-POWER CMOS FOR 3-VALUED LOGICMOUFTAH HT; SMITH KC.1982; IEE PROC., G; ISSN 0143-7089; GBR; DA. 1982; VOL. 129; NO 6; PP. 270-271; BIBL. 8 REF.Article

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ALGEBRAIC OPTIMISATION OF NAND-NOR SWITCHING CIRCUITS.TOSSER A; DUBUS D.1977; COMPUTER J.; G.B.; DA. 1977; VOL. 20; NO 1; PP. 73-77; BIBL. 12 REF.Article

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