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Results 1 to 25 of 1359

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Architecture and optical system design for TRANslucent smart pixel ARray (TRANSPAR) chipsCHEN, C.-H; HOANCA, B; KUZNIA, C. B et al.SPIE proceedings series. 1998, pp 316-319, isbn 0-8194-2949-XConference Paper

Was der HC12-Controller wirklich leistet : Systemvergleich des HC11- und HC12-Mikrocontrollers = Performance improvements from HC11 to HC12SIBIGTROTH, J.F & M. Feinwerktechnik, Mikrotechnik, Messtechnik. 1996, Vol 104, Num 11-12, pp 813-818, issn 0944-1018, 5 p.Article

Increasing microprocessor performance with tightly-coupled reconfigurable logic arraysSAWITZKI, S; GRATZ, A; SPALLEK, R. G et al.Lecture notes in computer science. 1998, pp 411-415, issn 0302-9743, isbn 3-540-64948-4Conference Paper

Improved layout of the odd-even sorting networkARTISHCHEV-ZAPOLOTSKY, Maria.Computer networks (1999). 2009, Vol 53, Num 14, pp 2387-2395, issn 1389-1286, 9 p.Article

Interconnect-limited VLSI architectureDALLY, W. J.IEEE 1999 international interconnect technology conference. 1999, pp 15-17, isbn 0-7803-5174-6Conference Paper

Satisfiability on reconfigurable hardwareABRAMOVICI, M; SAAB, D.Lecture notes in computer science. 1997, pp 448-456, issn 0302-9743, isbn 3-540-63465-7Conference Paper

An adaptive modular artificial neural network hourly load forecaster and its implementation at electric utilitiesKHOTANZAD, A; HWANG, R.-C; ABAYE, A et al.IEEE transactions on power systems. 1995, Vol 10, Num 3, pp 1716-1722, issn 0885-8950Article

A new encryption and hashing scheme for the security architecture for microprocessorsPLATTE, Jörg; DURAN DIAZ, Raul; NAROSKA, Edwin et al.Lecture notes in computer science. 2006, pp 120-129, issn 0302-9743, isbn 3-540-47820-5, 1Vol, 10 p.Conference Paper

Architecture and circuit techniques for a reconfigurable memory blockKEN MAI; HO, Ron; ALON, Elad et al.IEEE International Solid-State Circuits Conference. 2004, pp 500-501, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

The Imagine Stream ProcessorKAPASI, Ujval J; DALLY, William J; RIXNER, Scott et al.Proceedings, IEEE International Conference on Computer Design. 2002, pp 282-288, issn 1063-6404, isbn 0-7695-1700-5, 7 p.Conference Paper

Conception Testable de Circuits à Partir d'une Description Comportementale = Testable Design of Circuits starting with its Behavioral DescriptionFleury, Hervé; Robach, Chantal.2000, 128 p.Thesis

CMOS active pixel image sensor with CCD performanceMEYNANTS, G; DIERICKX, B; SCHEFFER, D et al.SPIE proceedings series. 1998, pp 68-76, isbn 0-8194-2862-0Conference Paper

The >S<puter : Introducing a novel concept for dispatching instructions using reconfigurable hardwareSIEMERS, C; MÖLLER, D. P. F.Lecture notes in computer science. 1998, pp 510-514, issn 0302-9743, isbn 3-540-64948-4Conference Paper

A structural approach for designing performance enhanced signal processors : A 1-MIPS GSM fullrate vocoder case studyWEISS, M. H; WALTHER, U; FETTWEIS, G. P et al.International conference on acoustics, speech, and signal processing. 1997, pp 4085-4088, isbn 0-8186-7919-0Conference Paper

Les Convertisseurs Statiques Percées dans les applications ― Révolution dans les architectures = Static converters: breakthrough for applications - Revolution for architecturesFOCH, Henri; MEYNARD, Thierry.La Revue 3 E I (Paris). 2011, Num 65, pp 60-68, issn 1252-770X, 9 p.Article

Efficient hardware for the tate pairing calculation in characteristic threeKERINS, T; MARNANE, W. P; POPOVICI, E. M et al.Lecture notes in computer science. 2005, pp 412-426, issn 0302-9743, isbn 3-540-28474-5, 15 p.Conference Paper

The impact of modem FPGA architectures on neural hardware : A case study of the TOTEM neural processorMCBADER, Stephanie; LEE, Peter; SARTORI, Alvise et al.International Joint Conference on Neural Networks. 2004, isbn 0-7803-8359-1, 4Vol, Vol4, 3149-3154Conference Paper

Area-time efficient between-class variance module for adaptive segmentation processTIAN, H; LAM, S. K; SRIKANTHAN, T et al.IEE proceedings. Vision, image and signal processing. 2003, Vol 150, Num 4, pp 263-269, issn 1350-245X, 7 p.Article

Rapid design of biorthogonal wavelet transformsMASUD, S; MCCANNY, J. V.IEE proceedings. Circuits, devices and systems. 2000, Vol 147, Num 5, pp 293-296, issn 1350-2409Article

A common transform engine for MPEG & AC3 audio decoderLAU, W; CHWU, A.IEEE transactions on consumer electronics. 1997, Vol 43, Num 3, pp 559-566, issn 0098-3063Article

Efficient VLSI architectures of adaptive equalizers for QAM/VSB transmissionSEUNG SOO CHAE; SUNG BUM PAN; GI HUN LEE et al.International conference on acoustics, speech, and signal processing. 1997, pp 4117-4120, isbn 0-8186-7919-0Conference Paper

Architecture électronique dédiée aux algorithmes rapides de segmentation basés sur la morphologie mathématique = Electronic architecture dedicated to fast segmentation algorithms based on mathematical morphologyLemonnier, Fabrice; Klein, J.-C.1996, 211 p.Thesis

An optimized S-Box circuit architecture for low power AES designMORIOKA, Sumio; SATOH, Akashi.Lecture notes in computer science. 2002, pp 172-186, issn 0302-9743, isbn 3-540-00409-2, 15 p.Conference Paper

A modern review of electronic computing circuits of the ENIACSCHNECK, P. B.Proceedings of the IEEE. 1997, Vol 85, Num 7, pp 1169-1171, issn 0018-9219Article

A mixed-signal VLSI circuit for skeletonization by grassfire transformationOLAH, M; MASA, P; LORINCZ, A et al.Lecture notes in computer science. 1997, pp 1205-1210, issn 0302-9743, isbn 3-540-63631-5Conference Paper

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