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Dynamic redundancy identification in automatic test generationABRAMOVICI, M; MILLER, D. T; ROY, R. K et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1992, Vol 11, Num 3, pp 404-407, issn 0278-0070Article

Zur schnellen Fehlersimulation in kombinatorischen Schaltungen = Sur l'accélération de la simulation des fautes dans les circuits combinatoires = On the acceleration of fault simulation in combinational circuitsANTREICH, K. J; SCHULZ, M. H.AEU. Archiv für Elektronik und Übertragungstechnik. 1986, Vol 40, Num 6, pp 355-362, issn 0001-1096Article

Processus dynamiques dans les automates à actions périodiquesLEVIN, V. I.Izvestiâ Akademii nauk SSSR. Tehničeskaâ kibernetika. 1986, Num 1, pp 81-93, issn 0002-3388Article

Propriétés des pannes du type «court-circuit» dans les circuits combinatoiresSAPOZHNIKOV, V. V; SAPOZHNIKOV, V. V; SAPOZHNIKOV, V. V; SAPOZHNIKOV, V. V; CHUKHONIN, V. M et al.Avtomatika i telemehanika. 1984, Num 3, pp 142-150, issn 0005-2310Article

Fault tolerant circuit using alternate-data retry strategyHASEGAWA, Y; NAITO, S.Systems, computers, controls. 1983, Vol 14, Num 1, pp 86-94, issn 0096-8765Article

Testability measures in pseudorandom testingERCOLANI, S; FAVALLI, M; DAMIANI, M et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1992, Vol 11, Num 6, pp 794-800, issn 0278-0070Article

On the complexity of estimating the size of a test setBALAKRISHNAN KRISHNAMURTHY; AKERS, S. B.IEEE transactions on computers. 1984, Vol 33, Num 8, pp 750-753, issn 0018-9340Article

A simple random test procedure for detection of single intermittent fault in combinational circuitsVIRUPAKSHIA, A. R; PRATAPA REDDY, V. C. V.IEEE transactions on computers. 1983, Vol 32, Num 6, pp 594-597, issn 0018-9340Article

Good controllability and observability do not guarantee good testabilitySAVIR, J.IEEE transactions on computers. 1983, Vol 32, Num 12, pp 1198-1200, issn 0018-9340Article

Pseudorandom testingWAGNER, K. D; CHIN, C. K; MCCLUSKEY, E. J et al.IEEE transactions on computers. 1987, Vol 36, Num 3, pp 332-343, issn 0018-9340Article

An efficient algorithm for single and multiple fault test sets generationSAILENDRANATH BANERJEE; RANAJITKISHORE THAKUR; PRAMODE RANJAN BHATTACHARJEE et al.International journal of computer mathematics. 1985, Vol 18, Num 2, pp 121-133, issn 0020-7160Article

Autocorrelation testing of combinational circuitsABORHEY, S.IEE proceedings. Part E. Computers and digital techniques. 1989, Vol 136, Num 1, pp 57-61, issn 0143-7062, 5 p.Article

Algorithme de recherche libre des défauts multiples dans les dispositifs combinatoiresKISELEV, V. V; KON, E. L.Avtomatika i telemehanika. 1984, Num 11, pp 155-163, issn 0005-2310Article

Universal tests for detection of input/output stuck-at and bridging faultsKARPOVSKY, M.IEEE transactions on computers. 1983, Vol 32, Num 12, pp 1194-1198, issn 0018-9340Article

Synthèse des tests de contrôle des circuits combinatoires arborescentsAJRAPETYAN, A. N.Izvestiâ Akademii nauk SSSR. Tehničeskaâ kibernetika. 1983, Num 5, pp 77-84, issn 0002-3388Article

Estimation of power dissipation in CMOS combinational circuits using boolean function manipulationDEVADAS, S; KEUTZER, K; WHITE, J et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1992, Vol 11, Num 3, pp 373-383, issn 0278-0070Article

Test exhaustif de circuits combinatoires = Exhaustive testing of combinatorial circuitsCOHEN, G; GODLEWSKI, P; KARPOVSKY, M et al.T.S. Traitement du signal. 1984, Vol 1, pp 223-226, no spéc. 2-2Article

Automated design of multiple-valued logic circuits by automatic theorem proving techniquesWOJCIECHOWSKI, W. S; WOJCIK, A. S.IEEE transactions on computers. 1983, Vol C.32, Num 9, pp 785-798, issn 0018-9340Article

Probabilistic fault location in combinational logic network using concepts of fault distance and input fealureDAS, S. R; JONE, W. B; FARES, G. E et al.Cybernetics and systems. 1989, Vol 20, Num 5, pp 385-399, issn 0196-9722, 15 p.Article

SOCRATES: a highly efficient automatic test pattern generation systemSCHULZ, M. H; TRISCHLER, E; SARFERT, T. M et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1988, Vol 7, Num 1, pp 126-137, issn 0278-0070Article

EKSIS - ein Programm zum Entwurf kombinatorischer Schaltungen durch iterative Ausnutzung von Symmetrieeingenschaften = EKSIS. Un programme pour l'étude de circuits combinatoires par la mise en valeur itérative de caractéristiques symétriques = A program for the design of combinatory circuits by iterative use of symmetry propertiesEHRSAM, O.Nachrichtentechnik. Elektronik. 1984, Vol 34, Num 12, pp 460-462, issn 0323-4657Article

Multiple fault detection in fanout-free combinational networksHARTMANN, C. R. P; DEBANY, W. H; VARSHNEY, P. K et al.Electronics Letters. 1984, Vol 20, Num 12, pp 516-517, issn 0013-5194Article

Test pattern generation using boolean statisfiabilityLARRABEE, T.IEEE transactions on computer-aided design of integrated circuits and systems. 1992, Vol 11, Num 1, pp 4-15, issn 0278-0070Article

A practical approach to fault simulation and test generation for bridging faultsABRAMOVICI, M; MENON, P. R.IEEE transactions on computers. 1985, Vol 34, Num 7, pp 658-663, issn 0018-9340Article

CMOS struck-open fault testabilityRAJSUMAN, R; MALAIYA, Y. K; JAYASUMANA, A. P et al.IEEE journal of solid-state circuits. 1989, Vol 24, Num 1, pp 193-194, issn 0018-9200, 2 p.Article

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