A 43Gb/s 2:1 Selector IC in 90nm CMOS technologyYAMAMOTO, Takuji; HORINAKA, Minoru; YAMAZAKI, Daisuke et al.IEEE International Solid-State Circuits Conference. 2004, pp 238-239, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

Leakage Power Characterization Considering Process VariationsROSSELLO, Jose L; DE BENITO, Carol; BOTA, Sebastia et al.Lecture notes in computer science. 2006, pp 66-74, issn 0302-9743, isbn 3-540-39094-4, 1Vol, 9 p.Conference Paper

Novel low-voltage fully-differential bufferFERRI, Giuseppe; GUERRINI, Nicola; SPERINI, Manolo et al.Proceedings of SPIE - the International Society for Optical Engineering. 2005, isbn 0-8194-5832-5, 2Vol, vol2, 994-1002Conference Paper

Few electron devices: Towards hybrid CMOS-SET integrated circuitsIONESCU, Adrian M; DECLERCQ, Michel J; MAHAPATRA, Santanu et al.Design automation conference. 2002, pp 88-93, isbn 1-58113-461-4, 6 p.Conference Paper

Local redesign for reliability of CMOS digital circuits under device degradationXIANGDONG XUAN; CHATTERJEE, Abhijit; SINGH, Adit D et al.IEEE international reliability physics symposium. 2004, pp 651-652, isbn 0-7803-8315-X, 1Vol, 2 p.Conference Paper

Test circuit for CMOS lead open detection by supply current testing under AC electric field applicationHASHIZUME, M; ICHIMIYA, M; YOTSUYANAGI, H et al.MWSCAS : Midwest symposium on circuits and systems. 2004, isbn 0-7803-8346-X, 3Vol, Vol I, 557-560Conference Paper

CMOS RF modeling, characterization and applicationsDEEN, M. Jamal; FJELDLY, Tor A.International journal of high speed electronics and systems. 2001, Vol 11, Num 4, 415 p.Serial Issue

A new compact model for external latchup : Electrostatic Discharge ReliabilityFARBIZ, Farzan; ROSENBAUM, Elyse.Microelectronics and reliability. 2009, Vol 49, Num 12, pp 1447-1454, issn 0026-2714, 8 p.Conference Paper

A differential current-mode sensing method for high-noise-immunity, single-ended register filesTZARTZANIS, Nestoras; WALKER, William W.IEEE International Solid-State Circuits Conference. 2004, pp 506-507, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

Polysilicon process development for fully integrated surface-micromachined accelerometer with CMOS electronicsKING, D. O; WARD, M. C. L; BRUNSON, K. M et al.Sensors and actuators. A, Physical. 1998, Vol 68, Num 1-3, pp 238-243, issn 0924-4247Conference Paper

Monolithic integration of GaAs devices with completely fabricated Si CMOS circuitsKAI MA; CHEN, Ray; MILLER, David A. B et al.Lasers and Electro-optics Society. 2004, isbn 0-7803-8557-8, 2Vol, Vol1, 230-231Conference Paper

CARACTÉRISATION ET MODÉLISATION DES CAPACITÉS PARASITES DUES AUX INTERCONNEXIONS EN TECHNOLOGIE CMOS FORTEMENT SUBMICRONIQUE = CHARACTERIZATION AND MODELLING OF INTERCONNECT PARASITIC CAPACITANCES IN DEEP SUBMICRONIC CMOS TECHNOLOGYBernard, David; Landrault, Christian.2000, 186 p.Thesis

CMOS sensor systemsHOSTICKA, B. J.Sensors and actuators. A, Physical. 1998, Vol 66, Num 1-3, pp 335-341, issn 0924-4247Conference Paper

Du radar à antennes réparties vers la peau intelligente : architectures de traitement du signal et liaisons optiques = From distributed antennas to intelligent skin : signal processing architectures and optical linksPLOUHINEC, R.REE. Revue de l'électricité et de l'électronique. 1995, Num 3, issn 1265-6534, 7, 67-72 [7 p.]Article

Quasi-static adiabatic logic 2N-2N2P2D familyHE, Y; TIAN, J; TAN, X et al.Electronics Letters. 2006, Vol 42, Num 16, pp 905-907, issn 0013-5194, 3 p.Article

High performance low power V_T-Wave-Pipeline CMOS circuit in PD/SOI technologyJOSHI, R. V; YEE, F; KIM, K et al.IEEE International SOI conference. 2002, pp 128-129, isbn 0-7803-7439-8, 2 p.Conference Paper

A silicon blue/UV selective stripe-shaped photodiodePAUCHARD, A; BESSE, P.-A; POPOVIC, R. S et al.Sensors and actuators. A, Physical. 1999, Vol 76, Num 1-3, pp 172-177, issn 0924-4247Conference Paper

Special Issue with Papers Selected from the Ultimate Integration on Silicon Conference, Ulis 2008SELMI, Luca; ESSENI, David; PALESTRI, Pierpaolo et al.Solid-state electronics. 2009, Vol 53, Num 4, issn 0038-1101, 68 p.Serial Issue

Test sans contact des Circuits Intégrés CMOS: Observabilité et Contrôlbilité du Latchup par Microscopie Electronique à Balayage et Microscopie à Emissio = Contactless Testing of CMOS Integrated Circuits: Observability and Controllability of Latchup by Scanning Electron Microscopy and Emission MicroscopyDilmahomed Bocus, Sadeck; Roche, Fernand Michel.1992, 201 p.Thesis

Designing digital subthreshold CMOS circuits using parallel transistor stacksMUKER, M; SHAMS, M.Electronics letters. 2011, Vol 47, Num 6, pp 372-374, issn 0013-5194, 3 p.Article

Gate substrate effect on RF CMOS device noiseXIONG, Y.-Z; SHI, J; LAN, N et al.Electronics Letters. 2007, Vol 43, Num 24, pp 1389-1390, issn 0013-5194, 2 p.Article

Statistical modelling and design guidelines of CMOS current referencesGIUSTOLISI, G; PALUMBO, G; GAIBOTTI, M et al.IEE proceedings. Circuits, devices and systems. 2006, Vol 153, Num 6, pp 559-564, issn 1350-2409, 6 p.Article

Compact static power model of complex CMOS gatesROSSELLO, Jose L; BOTA, Sebastia; SEGURA, Jaume et al.Lecture notes in computer science. 2005, pp 348-354, issn 0302-9743, isbn 3-540-29013-3, 7 p.Conference Paper

Noise-tolerant quantum MOS circuits using resonant tunneling devicesLI DING; MAZUMDER, Pinaki.IEEE transactions on nanotechnology. 2004, Vol 3, Num 1, pp 134-146, issn 1536-125X, 13 p.Article

A floating-body charge monitoring technique for partially depleted SOI technologyKUANG, J. B; SACCAMANGO, M. J; RATANAPHANYARAT, S et al.International journal of electronics. 2004, Vol 91, Num 11, pp 625-637, issn 0020-7217, 13 p.Article