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An improved model for the slewing behavior of opampsFENG WANG; RAMESH HARJANI.IEEE transactions on circuits and systems. 2, Analog and digital signal processing. 1995, Vol 42, Num 10, pp 679-681, issn 1057-7130Article

Efficient simulation of MOS circuitsERWE, R; TANABE, N.IEEE transactions on computer-aided design of integrated circuits and systems. 1991, Vol 10, Num 4, pp 541-544, issn 0278-0070Article

Chemosensors with pattern recognitionMULLER, R; HORNER, G.Siemens Forschungs- und Entwicklungsberichte. 1986, Vol 15, Num 3, pp 95-100, issn 0370-9736Article

Massively parallel switch-level simulation : a feasibility studyKRAVITZ, S. A; BRYANT, R. E; RUTENBAR, R. A et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1991, Vol 10, Num 7, pp 871-894, issn 0278-0070Article

Testing for stuck-at-faults in CMOS circuitsISMAEEL, A. A; NAJEM, Z.International journal of electronics. 1987, Vol 63, Num 5, pp 677-685, issn 0020-7217Article

The deskside supercomputerPEEPLES, J. W.Advances in cryogenic engineering. 1998, Vol 43, pp 849-855, issn 0065-2482, AConference Paper

Corrugation gratings for fast integrated complementary metal-oxide semiconductor photodetectors : implementation and diffraction anaysesCLYMER, B. D; GILLFILLAN, D.Applied optics. 1991, Vol 30, Num 30, pp 4390-4395, issn 0003-6935Article

The evolution of the MINIMOS mobility modelSELBERHERR, S; HÄNSCH, W; SEAVEY, M et al.AEU. Archiv für Elektronik und Übertragungstechnik. 1990, Vol 44, Num 3, pp 161-172, issn 0001-1096Article

Efficient power modelling approach of sequential circuits using recurrent neural networksHSIEH, W.-T; SHIUE, C.-C; LIU, C.-N. J et al.IEE proceedings. Computers and digital techniques. 2006, Vol 153, Num 2, pp 78-86, issn 1350-2387, 9 p.Article

A conception for reliability prediction and estimation of MOS integrated circuitsDIMITROV, S.Microelectronics and reliability. 1990, Vol 30, Num 1, pp 27-34, issn 0026-2714Article

Substrate bias effects on drain-induced barrier lowering in short channel PMOS devices at 77 KYAN, Z. X; DEEN, M. J.Cryogenics (Guildford). 1990, Vol 30, Num 12, pp 1160-1165, issn 0011-2275Article

Robust testing of CMOS logic circuitsJHA, N. K.Computers & electrical engineering. 1989, Vol 15, Num 1, pp 19-28, issn 0045-7906, 10 p.Article

Exhaustive testing of stuck-open faults in CMOS combinational circuitsBATE, J. A; MILLER, D. M.IEE proceedings. Part E. Computers and digital techniques. 1988, Vol 135, Num 1, pp 10-16, issn 0143-7062Article

A 16-bit CMOS D/A converter for digital audio applicationsYAMADA, Y; KAJITANI, M; OHGISHI, T et al.IEEE transactions on consumer electronics. 1987, Vol 33, Num 3, pp 267-274, issn 0098-3063Article

LDMOS linearity and reliabilityRICE, Jed.Microwave journal (Euro-global edition). 2002, Vol 45, Num 6, pp 64-72, issn 0192-6217, 7 p.Article

Hot electron and radiation induced degradation : Interaction in near micron MOS transistorANDHARE, P. N; NAHAR, R. K; WADHAWAN, O. P et al.SPIE proceedings series. 2000, pp 333-336, isbn 0-8194-3601-1Conference Paper

Strongly code-disjoint CMOS built-in intermediate voltage sensor for totally self-checking circuitsWONG, M. W. T; PANG, J. C. W; LEE, Y. S et al.International journal of electronics. 1999, Vol 86, Num 11, pp 1367-1375, issn 0020-7217Article

CMOS four-quadrant multiplier using triode transistors based on regulated cascode structureTSAY, J.-H; SHEN-IUAN LIU; JIANN-JONG CHEN et al.Electronics Letters. 1995, Vol 31, Num 12, pp 962-963, issn 0013-5194Article

Optoelectronic winner-take-all VLSI shunting neural networkKANE, J. S; KINCAID, T. G.IEEE transactions on neural networks. 1995, Vol 6, Num 5, pp 1275-1279, issn 1045-9227Article

Switched-current CMOS ternary logic circuitsSHOUSHA, A. H. M.International journal of electronics. 1995, Vol 79, Num 5, pp 617-625, issn 0020-7217Article

An input-free VT extractor circuit using a two-transistor differential amplifierJOHNSON, M. G.IEEE journal of solid-state circuits. 1993, Vol 28, Num 6, pp 704-705, issn 0018-9200Article

A fast timing simulator for MOS digital circuitsFAN ZOU.AEU. Archiv für Elektronik und Übertragungstechnik. 1990, Vol 44, Num 2, pp 148-152, issn 0001-1096Article

Comparison of two-phase latch configurations for pipelined processors in MOS VLSI : case study : a CMOS systolic multiplierSUMMERFIELD, S.IEE proceedings. Part G. Electronic circuits and systems. 1990, Vol 137, Num 4, pp 261-265, issn 0143-7089Article

MOS2: an efficient Monte Carlo simulator for MOS devicesSANGIORGI, E; RICCO, B; VENTURI, F et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1988, Vol 7, Num 2, pp 259-271, issn 0278-0070Article

Piecewise-linear timing delay modeling for digital CMOS circuitsAN-CHANG DENG.IEEE transactions on circuits and systems. 1988, Vol 35, Num 10, pp 1330-1334, issn 0098-4094Article

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