The influence of boundary locations on wiring capacitance simulationSHIGYO, N; FUKUDA, S; KATO, K et al.I.E.E.E. transactions on electron devices. 1989, Vol 36, Num 6, pp 1171-1174, issn 0018-9383, 4 p.Article

SPECIAL ISSUE ON THE 2011 SYMPOSIUM ON VLSI CIRCUITSMAKOTO NAGATA; VIVEK DE.IEEE journal of solid-state circuits. 2012, Vol 47, Num 4, issn 0018-9200, 272 p.Conference Proceedings

Special Issue on the 2010 Symposium on VLSI CircuitsAMERASEKERA, Ajith; NAGATA, Makoto.IEEE journal of solid-state circuits. 2011, Vol 46, Num 4, issn 0018-9200, 275 p.Conference Proceedings

The VLSI circuit test problem ― a tutorialHAWKINS, C. F; NAGLE, H. T; FRITZEMEIER, R. R et al.IEEE transactions on industrial electronics (1982). 1989, Vol 36, Num 2, pp 111-116, issn 0278-0046Article

A high-storage capacity content-addressable memory and its learning algorithmVERLEYSEN, M; SIRLETTI, B; VANDEMEULEBROECKE, A et al.IEEE transactions on circuits and systems. 1989, Vol 36, Num 5, pp 762-766, issn 0098-4094, 5 p.Article

Special Issue on the 2008 Symposium on VLSI CircuitsNAKAMURA, Katsu; MIZUNO, Masayuki.IEEE journal of solid-state circuits. 2009, Vol 44, Num 4, issn 0018-9200, 279 p.Conference Proceedings

ACM Great Lakes Symposium on VLSISTINE, James E; ZUKOWSKI, Charles A.Integration (Amsterdam). 2005, Vol 38, Num 3, issn 0167-9260, 211 p.Conference Proceedings

An associative memory based on hybrid SEED technologyGRIMM, G; FEY, D.SPIE proceedings series. 1998, pp 339-342, isbn 0-8194-2949-XConference Paper

Interconnection networks for sea-of-gates VLSI : Comparative analysis of performance and complexityMILUTINOVIC, D.International conference on microelectronic. 1997, pp 845-847, isbn 0-7803-3664-X, 2VolConference Paper

Genetic algorithm for embedding a complete graph in a hypercube with a VLSI applicationCHANDRASEKHARAM, R; VINOD, V. V; SUBRAMANIAN, S et al.Microprocessing and microprogramming. 1994, Vol 40, Num 8, pp 537-552, issn 0165-6074Article

VLSI reliability challenges : from device physics to wafer scale systemsTAKEDA, E; IKUZAKI, K; KATTO, H et al.Proceedings of the IEEE. 1993, Vol 81, Num 5, pp 653-674, issn 0018-9219Article

SATPOLY: a self-aligned tungsten on polysilicon process for CMOS VLSI applicationsMAN WONG; SARASWAT, K. C.I.E.E.E. transactions on electron devices. 1989, Vol 36, Num 7, pp 1355-1361, issn 0018-9383, 7 p.Article

Impact of the gate-drain overlapped device (GOLD) for deep submicrometer VLSIIZAWA, R; KURE, T; TAKEDA, E et al.I.E.E.E. transactions on electron devices. 1988, Vol 35, Num 12, pp 2088-2093, issn 0018-9383Article

Conducting transition metal oxides: possibilities for RuO₂ in VLSI metallizationKRUSIN-ELBAUM, L; WITTMER, M.Journal of the Electrochemical Society. 1988, Vol 135, Num 10, pp 2610-2614, issn 0013-4651Conference Paper

Applications of Hi-BiCMOS technologyNISHIO, Y; OGIUE, K; KADONO, S et al.Hitachi review. 1986, Vol 35, Num 5, pp 225-230, issn 0018-277XArticle

VLSI architecture of bit-serial quasicyclic encodersWANG, Q; EL QUIBALY, F. H; BHARGAVA, V. K et al.Electronics Letters. 1986, Vol 22, Num 22, pp 1170-1171, issn 0013-5194Article

SPECIAL ISSUE ON THE 2009 SYMPOSIUM ON VLSI CIRCUITSMIZUNO, Masayuki; AMERASEKERA, Ajith.IEEE journal of solid-state circuits. 2010, Vol 45, Num 4, issn 0018-9200, 245 p.Conference Proceedings

2006 Symposium on VLSI circuitsKOSONOCKY, Stephen V; YANO, Kazuo.IEEE journal of solid-state circuits. 2007, Vol 42, Num 4, issn 0018-9200, 232 p.Conference Proceedings

2004 Symposium on VLSI CircuitsGIESEKE, Bruce; KURODA, Tadahiro.IEEE journal of solid-state circuits. 2005, Vol 40, Num 4, issn 0018-9200, 226 p.Conference Proceedings

Algorithms for the Problem of K Maximum Sums and a VLSI Algorithm for the K Maximum Subarrays ProblemSUNG EUN BAE; TAKAOKA, Tadao.International Symposium on Parallel Architectures, Algorithms, and Networks. 2004, pp 247-253, isbn 0-7695-2135-5, 1Vol, 7 p.Conference Paper

VLSI technology and techniques for telecommunicationsHAMLIN, R. W.Annales des télécommunications. 1993, Vol 48, Num 3-4, pp 125-131, issn 0003-4347Article

A VLSI implementation of a correlator/digital-filter based on distributed arithmeticZOHAR, S.IEEE transactions on acoustics, speech, and signal processing. 1989, Vol 37, Num 1, pp 156-160, issn 0096-3518, 5 p.Article

A pipelined associative memory implemented in VLSICLARK, L. T; GRONDIN, R. O.IEEE journal of solid-state circuits. 1989, Vol 24, Num 1, pp 28-34, issn 0018-9200, 7 p.Article

A unified approach to layout wirabilityLIPSKI, W. JR; PREPARATA, F. P.Mathematical systems theory. 1987, Vol 19, Num 3, pp 189-203, issn 0025-5661Article

VLSI circuits and systems V (18-20 April 2011, Prague, Czech Republic)Riesgo, Teresa; Torre-Arnanz, Eduardo de la.Proceedings of SPIE, the International Society for Optical Engineering. 2011, Vol 8067, issn 0277-786X, isbn 978-0-8194-8656-1, 1 vol, isbn 978-0-8194-8656-1Conference Proceedings