Pascal and Francis Bibliographic Databases

Help

Search results

Your search

kw.\*:("Circuito combinatorio")

Document Type [dt]

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Publication Year[py]

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Discipline (document) [di]

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Language

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Author Country

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Results 1 to 25 of 253

  • Page / 11
Export

Selection :

  • and

Zur schnellen Fehlersimulation in kombinatorischen Schaltungen = Sur l'accélération de la simulation des fautes dans les circuits combinatoires = On the acceleration of fault simulation in combinational circuitsANTREICH, K. J; SCHULZ, M. H.AEU. Archiv für Elektronik und Übertragungstechnik. 1986, Vol 40, Num 6, pp 355-362, issn 0001-1096Article

Pseudorandom testingWAGNER, K. D; CHIN, C. K; MCCLUSKEY, E. J et al.IEEE transactions on computers. 1987, Vol 36, Num 3, pp 332-343, issn 0018-9340Article

An efficient algorithm for single and multiple fault test sets generationSAILENDRANATH BANERJEE; RANAJITKISHORE THAKUR; PRAMODE RANJAN BHATTACHARJEE et al.International journal of computer mathematics. 1985, Vol 18, Num 2, pp 121-133, issn 0020-7160Article

Autocorrelation testing of combinational circuitsABORHEY, S.IEE proceedings. Part E. Computers and digital techniques. 1989, Vol 136, Num 1, pp 57-61, issn 0143-7062, 5 p.Article

Probabilistic fault location in combinational logic network using concepts of fault distance and input fealureDAS, S. R; JONE, W. B; FARES, G. E et al.Cybernetics and systems. 1989, Vol 20, Num 5, pp 385-399, issn 0196-9722, 15 p.Article

SOCRATES: a highly efficient automatic test pattern generation systemSCHULZ, M. H; TRISCHLER, E; SARFERT, T. M et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1988, Vol 7, Num 1, pp 126-137, issn 0278-0070Article

CMOS struck-open fault testabilityRAJSUMAN, R; MALAIYA, Y. K; JAYASUMANA, A. P et al.IEEE journal of solid-state circuits. 1989, Vol 24, Num 1, pp 193-194, issn 0018-9200, 2 p.Article

Fast test generation and partial testing for combinational logic circuitsLIU, J.International journal of electronics. 1987, Vol 62, Num 5, pp 739-746, issn 0020-7217Article

Interfacing bi-phase incremental encodersTEZ, E. S.IEEE transactions on industrial electronics (1982). 1986, Vol 33, Num 3, pp 337-338, issn 0278-0046Article

Removing multiple redundancies in combinational circuitsCHANG, Shih-Chieh; CHENG, David Ihsin; YEH, Ching-Wei et al.IEE proceedings. Computers and digital techniques. 2002, Vol 149, Num 1, pp 1-8, issn 1350-2387Article

Logical relations in circuit verificationINDRIKA, M.Lecture notes in computer science. 1999, pp 151-162, issn 0302-9743, isbn 3-540-66856-XConference Paper

Pitfalls in delay fault testingPIERZYNSKA, A; PILARSKI, S.IEEE transactions on computer-aided design of integrated circuits and systems. 1997, Vol 16, Num 3, pp 321-329, issn 0278-0070Article

Strongly code disjoint checkersNICOLAIDIS, M; COURTOIS, B.IEEE transactions on computers. 1988, Vol 37, Num 6, pp 751-756, issn 0018-9340Article

Self: a self-timed systems design techniqueLAU, C. H.Electronics Letters. 1987, Vol 23, Num 6, pp 269-270, issn 0013-5194Article

Bounding signal probabilities in combinational circuitsMARKOWSKY, G.IEEE transactions on computers. 1987, Vol 36, Num 10, pp 1247-1251, issn 0018-9340Article

Functional complexity estimation for large combinational circuitsABORHEY, S.IEE proceedings. Computers and digital techniques. 2002, Vol 149, Num 2, pp 39-45, issn 1350-2387Article

A stepwise-overlapped parallel simulated annealing algorithmYOUNGTAK KIM; MYUNGHWAN KIM.Integration (Amsterdam). 1990, Vol 10, Num 1, pp 39-54, issn 0167-9260, 16 p.Article

A generalized fault simulator for combinatorial logic circuitsRAINA, R; RAJASHEKHARA, T. N.Computers & electrical engineering. 1989, Vol 15, Num 3-4, pp 89-96, issn 0045-7906, 8 p.Article

Test length for pseudorandom testingCHIN, C. K; MCCLUSKEY, E. J.IEEE transactions on computers. 1987, Vol 36, Num 2, pp 252-256, issn 0018-9340Article

A computer-aided technique for fault detection in combinational circuitsSURESH RAI; RAJIV JAIN.Microelectronics and reliability. 1987, Vol 27, Num 2, pp 263-265, issn 0026-2714Article

A cubical logic circuit modelling for reliability studiesDOKOUZGIANNIS, S. P; KONTOLEON, J. M.Microelectronics and reliability. 1987, Vol 27, Num 5, pp 823-831, issn 0026-2714Article

Logic circuit speeding up through multiplexingTOMASHAU, V. F.Lecture notes in computer science. 1999, pp 438-443, issn 0302-9743, isbn 3-540-66457-2Conference Paper

Using D-algebra to generate tests for m-logic combinational circuitsTABAKOW, I. G.International journal of electronics. 1993, Vol 75, Num 5, pp 897-906, issn 0020-7217Article

On random testing for combinational circuits with a high measure of confidenceDAS, S. R; JONE, W.-B.IEEE transactions on systems, man, and cybernetics. 1992, Vol 22, Num 4, pp 748-754, issn 0018-9472Article

Multiple fault detection using single-fault testsKUO, T.-Y; WANG, J.-F; LEE, J.-Y et al.Electronics Letters. 1991, Vol 27, Num 15, pp 1329-1330, issn 0013-5194Article

  • Page / 11