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ATILA, a program to generate test patterns for scan testable logicSMITH, P. J.GEC journal of research. 1988, Vol 6, Num 3, pp 147-151, issn 0264-9187Article

Development of a user friendly gate-level logic simulatorSTIGALL, P. D; KUMAR SHIV.Computers & electrical engineering. 1987, Vol 13, Num 3-4, pp 147-167, issn 0045-7906Article

Einsatzerfahrungen und Weiterentwicklung des Gate-Array-Entwurfssystems PC-GAD = Experiences obtained and future development of the gate assay design system PC-GADPAULIUK, J.Wissenschaftliche Zeitschrift der Technischen Universität Karl-Marx-Stadt. 1989, Vol 31, Num 4, pp 521-527, issn 0863-0615, 7 p.Article

A method for generating weighted random test patternsWAICUKAUSKI, J. A; LINDBLOOM, E; EICHELBERGER, E. B et al.IBM journal of research and development. 1989, Vol 33, Num 2, pp 149-161, issn 0018-8646, 13 p.Article

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Error-sevure and error-propagating concepts for strongly fault-secure systemsNANYA, T; KAWAMURA, T.Systems and computers in Japan. 1987, Vol 18, Num 3, pp 11-18, issn 0882-1666Article

Evaluating the signal-reliability of logic circuitsKYUNG-SHIK KOH.IEEE transactions on reliability. 1985, Vol 34, Num 3, pp 233-235, issn 0018-9529Article

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Low-voltage-swing logic circuits for a 7GHz X86 integer coreDANIEL J., Deleganes; MICAH, Barany; GEORGE, Geannopoulos et al.IEEE International Solid-State Circuits Conference. 2004, pp 154-155, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

MUSTANG: state assignment of finite state machines targeting multilevel logic implementationsSRINIVAS DEVADAS; HI-KEUNG MA; NEWTON, A. R et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1988, Vol 7, Num 12, pp 1290-1300, issn 0278-0070Article

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Comparative rating of logic active devicesGIACOLETTO, L. J.I.E.E.E. transactions on electron devices. 1989, Vol 36, Num 11, pp 2592-2593, issn 0018-9383, 2 p., part 1Article

Tri-state map for the minimisation of exclusive-OR switching functionsTRAN, A.IEE proceedings. Part E. Computers and digital techniques. 1989, Vol 136, Num 1, pp 16-21, issn 0143-7062, 6 p.Article

Multivalued logic integral calculusGIUMA, T. A; ABDOLLAH KATBAB.International journal of electronics. 1988, Vol 65, Num 6, pp 1051-1066, issn 0020-7217Article

Enzyme-free nucleic acid logic circuitsSEELIG, Georg; SOLOVEICHIK, David; ZHANG, David Yu et al.Science (Washington, D.C.). 2006, Vol 314, Num 5805, pp 1585-1588, issn 0036-8075, 4 p.Article

Partitioning of logic circuits for exhaustive testingLALA, P. K; TAO, D. L.International journal of electronics. 1990, Vol 69, Num 2, pp 225-231, issn 0020-7217Article

Analysis of a double-latch synchroniser circuitJACKSON, T. A; ALBICKI, A.Electronics Letters. 1989, Vol 25, Num 5, pp 315-316, issn 0013-5194, 2 p.Article

Description and verification of input constraints and input-output specifications of logic circuitsKIMURA, S; YAJIMA, S.Systems and computers in Japan. 1987, Vol 18, Num 7, pp 29-42, issn 0882-1666Article

Symmetric fanout-free functionsSTOJMENOVIC, I; MIYAKAWA, M.Transactions of the Institute of Electronics and Communication Engineers of Japan. Section E. 1987, Vol 70, Num 6, pp 548-549, issn 0387-236XArticle

Technique to study multiple-valued logic in courses on modern logic design of discrete devicesLEVASHENKO, V; ZAITSEVA, E; SANKO, A et al.International conference on new information technologies in education. 1996, pp 329-338, isbn 83-86359-44-7Conference Paper

High-speed divider using GaAs ECL/CML gate arrayTOPHAM, P. J; PARTON, J. G; GOLDER, M. J et al.Electronics Letters. 1989, Vol 25, Num 7, pp 432-433, issn 0013-5194, 2 p.Article