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IUMRS-ICEM-2010. Materials and Devices for Future Logic TechnologyCHOI, Rino; CHEOL SEONG HWANG; YOUNG-BAE PARK et al.Microelectronic engineering. 2012, Vol 89, issn 0167-9317, 143 p.Conference Proceedings

Multi-valued logic systemsHAWKEN, R. E.International journal of electronics. 1989, Vol 67, Num 5, issn 0020-7217, 142 p.Serial Issue

Application of AlGaAs/GaAs HBT's to high-speed CML logic family fabricationMOHAMMAD MADIHIAN; TANAKA, S.-I; HAYAMA, N et al.I.E.E.E. transactions on electron devices. 1989, Vol 36, Num 4, pp 625-631, issn 0018-9383, 7 p.Article

On the approach of the stationary state in Kauffman's random Boolean networkHILHORST, H. J; NIJMEIJER, M.Journal de physique (Paris). 1987, Vol 48, Num 2, pp 185-191, issn 0302-0738Article

ATILA, a program to generate test patterns for scan testable logicSMITH, P. J.GEC journal of research. 1988, Vol 6, Num 3, pp 147-151, issn 0264-9187Article

Development of a user friendly gate-level logic simulatorSTIGALL, P. D; KUMAR SHIV.Computers & electrical engineering. 1987, Vol 13, Num 3-4, pp 147-167, issn 0045-7906Article

Einsatzerfahrungen und Weiterentwicklung des Gate-Array-Entwurfssystems PC-GAD = Experiences obtained and future development of the gate assay design system PC-GADPAULIUK, J.Wissenschaftliche Zeitschrift der Technischen Universität Karl-Marx-Stadt. 1989, Vol 31, Num 4, pp 521-527, issn 0863-0615, 7 p.Article

A method for generating weighted random test patternsWAICUKAUSKI, J. A; LINDBLOOM, E; EICHELBERGER, E. B et al.IBM journal of research and development. 1989, Vol 33, Num 2, pp 149-161, issn 0018-8646, 13 p.Article

Parity predictor for shifting-output addersVASSILIADIS, S; PUTRINO, M; SCHWARZ, E. M et al.Electronics Letters. 1989, Vol 25, Num 6, pp 422-424, issn 0013-5194, 3 p.Article

Error-sevure and error-propagating concepts for strongly fault-secure systemsNANYA, T; KAWAMURA, T.Systems and computers in Japan. 1987, Vol 18, Num 3, pp 11-18, issn 0882-1666Article

Evaluating the signal-reliability of logic circuitsKYUNG-SHIK KOH.IEEE transactions on reliability. 1985, Vol 34, Num 3, pp 233-235, issn 0018-9529Article

Multilevel logical networksKARPOVSKY, M.IEEE transactions on computers. 1987, Vol 36, Num 2, pp 215-226, issn 0018-9340Article

Hard magnetic cylindrical domains (HMD) as elements of multistate logicSZKODNY, T.Bulletin of the Polish Academy of Sciences. Technical sciences. 1984, Vol 32, Num 5-6, pp 333-339, issn 0239-7528Article

Properties of wired logicKAMBAYASHI, Y; MUROGA, S.IEEE transactions on computers. 1986, Vol 35, Num 6, pp 550-563, issn 0018-9340Article

Correction to : evaluating fault trees (AND & OR gates only) with repeated eventsBROWN, K. S.IEEE transactions on reliability. 1991, Vol 40, Num 1, issn 0018-9529, p. 19Article

Removal of sign-extension circuitry from booth's algorithm multiplier-accumulatorsBURGESS, N.Electronics Letters. 1990, Vol 26, Num 17, pp 1413-1415, issn 0013-5194Article

Use of linearisation and spectral techniques in input and output compaction testing of digital networksHURST, S. L.IEE proceedings. Part E. Computers and digital techniques. 1989, Vol 136, Num 1, pp 48-56, issn 0143-7062, 9 p.Article

Minimization of multivalued logic functionsGUIMA, T. A; TAPIA, M. A.International journal of electronics. 1987, Vol 63, Num 2, pp 171-183, issn 0020-7217Article

Low-voltage-swing logic circuits for a 7GHz X86 integer coreDANIEL J., Deleganes; MICAH, Barany; GEORGE, Geannopoulos et al.IEEE International Solid-State Circuits Conference. 2004, pp 154-155, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

MUSTANG: state assignment of finite state machines targeting multilevel logic implementationsSRINIVAS DEVADAS; HI-KEUNG MA; NEWTON, A. R et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1988, Vol 7, Num 12, pp 1290-1300, issn 0278-0070Article

RNA used to control a DNA rotary nanomachineHONG ZHONG; SEEMAN, Nadrian C.Nano letters (Print). 2006, Vol 6, Num 12, pp 2899-2903, issn 1530-6984, 5 p.Article

Neue Möglichkeiten der zeitlichen Logiksimulation im Gate-Array-CAD-System U5300 = New capabilities of logic simulation in gate array CAO system U 5300FÜGERT, E; MAYAS, R; PORSCH, U et al.Wissenschaftliche Zeitschrift der Technischen Universität Karl-Marx-Stadt. 1989, Vol 31, Num 4, pp 512-520, issn 0863-0615, 9 p.Article

Comparative rating of logic active devicesGIACOLETTO, L. J.I.E.E.E. transactions on electron devices. 1989, Vol 36, Num 11, pp 2592-2593, issn 0018-9383, 2 p., part 1Article

Tri-state map for the minimisation of exclusive-OR switching functionsTRAN, A.IEE proceedings. Part E. Computers and digital techniques. 1989, Vol 136, Num 1, pp 16-21, issn 0143-7062, 6 p.Article

Multivalued logic integral calculusGIUMA, T. A; ABDOLLAH KATBAB.International journal of electronics. 1988, Vol 65, Num 6, pp 1051-1066, issn 0020-7217Article

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