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Offset-compensated switched-capacitor delay circuit that is insensitive to stray capacitance and to capacitor mismatchDABROWSKI, A; MENZI, U; MOSCHYTZ, G. S et al.Electronics Letters. 1989, Vol 25, Num 10, pp 623-625, issn 0013-5194, 3 p.Article

Analysis and attenuation proposal in ground bounceZENTENO, Antonio; CHAMPAC, Victor H; RENOVELL, Michell et al.Asian test symposium. 2004, pp 460-463, isbn 0-7695-2235-1, 1Vol, 4 p.Conference Paper

Statistical static timing analysis using symbolic event propagationMONDAL, A; CHAKRABARTI, P. P; DASGUPTA, P et al.IET circuits, devices & systems (Print). 2007, Vol 1, Num 4, pp 283-291, issn 1751-858X, 9 p.Article

PC sampling oscillograph for subnanosecond time regionCERVEN, J; KUKUCA, R.Electronics Letters. 1990, Vol 26, Num 23, pp 1950-1952, issn 0013-5194Article

Sine-wave crossing technique as a basis for a sinusoidal phase shifterFYATH, R. S; HASSAN, A. K.International journal of electronics. 1993, Vol 75, Num 4, pp 655-664, issn 0020-7217Article

0.1 ps resolution delay circuit for waveform measurement in the stroboscopic scanning electron microscopeFUJIOKA, H; KUNIZAWA, H; URA, K et al.Journal of physics. E. Scientific instruments. 1986, Vol 19, Num 12, pp 1025-1026, issn 0022-3735Article

An externally triggered circuit producing digitally controlled delays with sub-nanosecond step sizePESOR, J. Z; LAWRANCE, W. D.Measurement science & technology (Print). 1990, Vol 1, Num 1, pp 24-28, issn 0957-0233Article

Implementation of wideband integer and fractional delay elementMURPHY, N. P; KRUKOWSKI, A; KALE, I et al.Electronics Letters. 1994, Vol 30, Num 20, pp 1658-1659, issn 0013-5194Article

Difference ratio of a function and an analysis of signal time delay circuitsGOLUB, V. S.Soviet journal of communications technology & electronics. 1991, Vol 36, Num 11, pp 115-117, issn 8756-6648Article

On the use of redundant pyrotechnic delaysYANIV, A.Propellants, explosives, pyrotechnics. 1988, Vol 13, Num 4, pp 106-110, issn 0721-3115Article

Extracting exact time bounds from logical proofsFERRARI, Mauro; FIORENTINI, Camillo; ORNAGHI, Mario et al.Lecture notes in computer science. 2002, pp 245-265, issn 0302-9743, isbn 3-540-43915-3, 21 p.Conference Paper

Design-for-testability to achieve complete coverage of delay faults in standard full scan circuitsPOMERANZ, Irith; REDDY, Sudhakar M.Journal of systems architecture. 2001, Vol 47, Num 3-4, pp 357-373, issn 1383-7621Article

Nonlinear growth stage of the cyclotron instability of a beam in a retarding structureKAPCHINSKII, M. I; YUDIN, L. A; MCNEILL, D. H et al.Technical physics. 1993, Vol 38, Num 11, pp 994-1000, issn 1063-7842Article

Switched-capacitor delay system suitable for cascaded multi-stagesOGIHARA, A; HAMANO, H; YONEDA, S et al.International journal of electronics. 1990, Vol 68, Num 3, pp 413-421, issn 0020-7217Article

Simplified data transmission tracking loop-a new NRZ maximum likelihood symbol synchroniserCHIU, J.-H; LEE, L.-S.Electronics Letters. 1990, Vol 26, Num 17, pp 1417-1419, issn 0013-5194Article

A 10-ps resolution, process-insensitive timing generator ICOTSUJI, T.-I; NARUMI, N.IEEE journal of solid-state circuits. 1989, Vol 24, Num 5, pp 1412-1418, issn 0018-9200Article

Measurement system for thermal drift of propagation time in fast pulse circuitsWIECZOREK, Piotr Z.Proceedings of SPIE, the International Society for Optical Engineering. 2006, issn 0277-786X, isbn 0-8194-6431-7, vol2, 63472F.1-63472F.7Conference Paper

Synchronized subthreshold oscillations and phase coding in a network model of the entorhinal cortexIGARASHI, Jun; YOSHIDA, Motoharu; TATENO, Katsumi et al.International Joint Conference on Neural Networks. 2004, isbn 0-7803-8359-1, 4Vol, Vol4, 3119-3123Conference Paper

What does robust testing a subset of paths, tell us about the untested paths in the circuit?SHARMA, Manish; PATEL, Janak H.IEEE VLSI test symposium. 2004, pp 31-36, isbn 0-7695-2134-7, 1Vol, 6 p.Conference Paper

Continuously variable signal delays with ultrasoundKOST, A; GAVENDA, J. D.IEEE transactions on ultrasonics, ferroelectrics, and frequency control. 1986, Vol 33, Num 6, pp 679-680, issn 0885-3010Article

Novel sizing algorithm for yield improvement under process variation in nanometer technologySEUNG HOON CHOI; PAUL, Bipul C; ROY, Kaushik et al.Design automation conference. 2004, pp 454-459, isbn 1-58113-828-8, 6 p.Conference Paper

High-speed and low-cost reverse converters for the (2n - 1, 2n, 2n + 1) moduli setPREMKUMAR, A. B; BHARDWAJ, M; SRIKANTHAN, T et al.IEEE transactions on circuits and systems. 2, Analog and digital signal processing. 1998, Vol 45, Num 7, pp 903-908, issn 1057-7130Article

Inexpensive home computer used as a versatile digital delay generatorPARDON, A; PEETERS, J.Review of scientific instruments. 1988, Vol 59, Num 11, pp 2499-2500, issn 0034-6748Article

Weighted Hamming distance for PUF performance evaluationSADR, A; ZOLFAGHARI-NEJAD, M.Electronics letters. 2013, Vol 49, Num 22, pp 1376-1378, issn 0013-5194, 3 p.Article

Post-fabrication clock timing adjustment for digital LSIs with genetic algorithms ensuring timing marginsMURAKAWA, Masahiro; TAKAHASHI, Eiichi; SUSA, Tatsuya et al.International Conference on Systems, Man and Cybernetics. 2004, isbn 0-7803-8566-7, vol4, 3670-3674Conference Paper

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