Pascal and Francis Bibliographic Databases

Help

Search results

Your search

kw.\*:("Circuito secuencial")

Document Type [dt]

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Publication Year[py]

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Discipline (document) [di]

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Language

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Author Country

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Results 1 to 25 of 662

  • Page / 27
Export

Selection :

  • and

Techniques for finding Xs in test sequences for sequential circuits and applications to test length/power reductionHIGAMI, Yoshinobu; KAJIHARA, Seiji; KOBAYASHI, Sin-Ya et al.Asian test symposium. 2004, pp 46-49, isbn 0-7695-2235-1, 1Vol, 4 p.Conference Paper

A novel design of sequential network to facilitate fault detectionBHATTACHARJEE, P. R; BASU, S. K; PAUL, J. C et al.Proceedings of the IEEE. 1987, Vol 75, Num 7, pp 971-972, issn 0018-9219Article

Variabilité de calculs et débordements de décodeurs séquentiels à pile = Computational variability and overflows of stack sequential decodersHACCOUN, D.T.S. Traitement du signal. 1986, Vol 3, Num 3, pp 127-143Article

A state assignment approach to asynchronous CMOS circuit designKANTABUTRA, V; ANDREOU, A. G.IEEE transactions on computers. 1994, Vol 43, Num 4, pp 460-469, issn 0018-9340Article

A tool for hierarchical test generationKRÜGER, G.IEEE transactions on computer-aided design of integrated circuits and systems. 1991, Vol 10, Num 4, pp 519-524, issn 0278-0070Article

A graph theoretic approach for state assignment of asynchronous sequential machinesDATTA, P. K; BANDYOPADHYAY, S. K; CHOUDHURY, A. K et al.International journal of electronics. 1988, Vol 65, Num 6, pp 1067-1075, issn 0020-7217Article

Specifying and verifying imprecise sequential datapaths by arithmetic transformsRADECKA, Katarzyna; ZILIC, Zeliko.Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design. 2002, pp 128-131, issn 1092-3152, isbn 0-7803-7607-2, 4 p.Conference Paper

Probabilistic modeling and fault analysis in sequential logic using computer simulationDAS, S. R; JONE, W. B; WONG, K. L et al.IEEE transactions on systems, man, and cybernetics. 1990, Vol 20, Num 2, pp 490-498, issn 0018-9472Article

The impact of clock gating schemes on the power dissipation of synthesizable register filesMUELLER, M; WORTMANN, A; SIMON, S et al.IEEE International Symposium on Circuits and Systems. 2004, pp 609-612, isbn 0-7803-8251-X, 4 p.Conference Paper

B2M : A semantic based tool for BLIF hardware descriptionsBASIN, David; FRIEDRICH, Stefan; MÖDERSHEIM, Sebastian et al.Lecture notes in computer science. 2000, pp 91-107, issn 0302-9743, isbn 3-540-41219-0Conference Paper

Decision problems for interacting finite state machinesDRUSINSKY-YORESH, D.IEEE transactions on computer-aided design of integrated circuits and systems. 1991, Vol 10, Num 12, pp 1576-1579, issn 0278-0070Article

Reliable VLSI sequential controllersWHITAKER, S. R; MAKI, G. K; MANJUNATH SHAMANNA et al.International journal of electronics. 1991, Vol 71, Num 4, pp 609-620, issn 0020-7217Article

Self: a self-timed systems design techniqueLAU, C. H.Electronics Letters. 1987, Vol 23, Num 6, pp 269-270, issn 0013-5194Article

A hardware accelerator based system for ATPG of sequential circuitsPORTELLI, B.Computer-aided engineering journal. 1987, Vol 4, Num 3, pp 140-144, issn 0263-9327Article

A signed bit-sequential multiplierRHYNE, T; STRADER, N. R. II.IEEE transactions on computers. 1986, Vol 35, Num 10, pp 896-901, issn 0018-9340Article

Scan chain configuration based X-filling for low power and high quality testingCHEN, Z; FENG, J; XIANG, D et al.IET computers & digital techniques (Print). 2010, Vol 4, Num 1, pp 1-13, issn 1751-8601, 13 p.Article

An extended class of sequential circuits with combinational test generation complexityINOUE, Michiko; JINNO, Chikateru; FUJIWARA, Hideo et al.Proceedings, IEEE International Conference on Computer Design. 2002, pp 200-205, issn 1063-6404, isbn 0-7695-1700-5, 6 p.Conference Paper

Designing sequential systems with fuzzy J-K flip-flopsHIROTA, K; PEDRYCZ, W.Fuzzy sets and systems. 1991, Vol 39, Num 3, pp 261-278, issn 0165-0114, 18 p.Article

Test generation and verification for highly sequential circuitsABHIJIT GHOSH; SRINIVAS DEVADAS; NEWTON, A. R et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1991, Vol 10, Num 5, pp 652-667, issn 0278-0070Article

Automatic verification of sequential circuits using temporal logicBROWNE, M. C; CLARKE, E. M; DILL, D. L et al.IEEE transactions on computers. 1986, Vol 35, Num 12, pp 1035-1044, issn 0018-9340Article

An observability enhancement approach for improved testability and at-speed testRUDNICK, E. M; CHICKERMANE, V; PATEL, J. H et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1994, Vol 13, Num 8, pp 1051-1056, issn 0278-0070Article

An algorithm to generate complete test sets for stuck-at faults in combinational logic circuitsTUNG, L. J; KERNS, D. V.Journal of the Franklin Institute. 1988, Vol 325, Num 1, pp 133-142, issn 0016-0032Article

Shift register sequence segmentation using random segmentation pointsNARRAWAY, J. J.Electronics Letters. 1988, Vol 24, Num 19, pp 1193-1194, issn 0013-5194Article

Modified transition matrix and fault testing in sequential logic circuits under random stimuli with a specified measure of confidenceDAS, S. R; JONE, W. B.Cybernetics and systems. 1986, Vol 17, Num 1, pp 1-12, issn 0196-9722Article

TEST INTÉGRÉ DES CIRCUITS SÉQUENTIELS = BUILT-IN SELF-TEST FOR SEQUENTIAL CIRCUITSPetitqueux, Aurélia; Landrault, Christian.2000, 176 p.Thesis

  • Page / 27