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An efficient algorithm for single and multiple fault test sets generationSAILENDRANATH BANERJEE; RANAJITKISHORE THAKUR; PRAMODE RANJAN BHATTACHARJEE et al.International journal of computer mathematics. 1985, Vol 18, Num 2, pp 121-133, issn 0020-7160Article

Zur schnellen Fehlersimulation in kombinatorischen Schaltungen = Sur l'accélération de la simulation des fautes dans les circuits combinatoires = On the acceleration of fault simulation in combinational circuitsANTREICH, K. J; SCHULZ, M. H.AEU. Archiv für Elektronik und Übertragungstechnik. 1986, Vol 40, Num 6, pp 355-362, issn 0001-1096Article

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Fault tolerant circuit using alternate-data retry strategyHASEGAWA, Y; NAITO, S.Systems, computers, controls. 1983, Vol 14, Num 1, pp 86-94, issn 0096-8765Article

Autocorrelation testing of combinational circuitsABORHEY, S.IEE proceedings. Part E. Computers and digital techniques. 1989, Vol 136, Num 1, pp 57-61, issn 0143-7062, 5 p.Article

Algorithme de recherche libre des défauts multiples dans les dispositifs combinatoiresKISELEV, V. V; KON, E. L.Avtomatika i telemehanika. 1984, Num 11, pp 155-163, issn 0005-2310Article

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Automated design of multiple-valued logic circuits by automatic theorem proving techniquesWOJCIECHOWSKI, W. S; WOJCIK, A. S.IEEE transactions on computers. 1983, Vol C.32, Num 9, pp 785-798, issn 0018-9340Article

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