kw.\*:("Concurrent error detection")
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Reliable floating-point arithmetic algorithms for error-coded operandsJIEN-CHUNG LO.IEEE transactions on computers. 1994, Vol 43, Num 4, pp 400-412, issn 0018-9340Article
A systematic approach for designing concurrent error-detecting systolic arrays using redundancyZHANG, C. N; LI, H. F; JAYAKUMAR, R et al.Parallel computing. 1993, Vol 19, Num 7, pp 745-764, issn 0167-8191Article
A totally self-checking checker for a parallel unordered coding schemeBURNS, S. W; KHA, N. K.IEEE transactions on computers. 1994, Vol 43, Num 4, pp 490-495, issn 0018-9340Article
Concurrent Error Detection in Bit-Serial Normal Basis Multiplication Over GF(2m) Using Multiple Parity Prediction SchemesLEE, Chiou-Yng; PRAMOD KUMAR MEHER; JAGDISH CHANDRA PATRA et al.IEEE transactions on very large scale integration (VLSI) systems. 2010, Vol 18, Num 8, pp 1234-1238, issn 1063-8210, 5 p.Article
Berger check prediction for array multipliers and array dividersJIEN-CHUNG LO; SUCHAI THANAWASTIEN; RAO, T. R. N et al.IEEE transactions on computers. 1993, Vol 42, Num 7, pp 892-896, issn 0018-9340Article
On concurrent detection of errors in polynomial basis multiplicationBAYAT-SARMADI, Siavash; ANWAR HASAN, M.IEEE transactions on very large scale integration (VLSI) systems. 2007, Vol 15, Num 4, pp 413-426, issn 1063-8210, 14 p.Article
Exploiting instruction-level parallelism for integrated control-flow monitoringSCHUETTE, M. A; SHEN, J. P.IEEE transactions on computers. 1994, Vol 43, Num 2, pp 129-140, issn 0018-9340Article
Design of self-testing checkers for borden codesPIESTRAK, S. J.IEEE transactions on computers. 1996, Vol 45, Num 4, pp 461-469, issn 0018-9340Article
An optimal graph-construction approach to placing program signatures for signature monitoringWILKEN, K. D.IEEE transactions on computers. 1993, Vol 42, Num 11, pp 1372-1381, issn 0018-9340Article
Optimal desing of checks for error detection and location in fault-tolerant multiprocessor systemsSITARAMAN, R. K; JHA, N. K.IEEE transactions on computers. 1993, Vol 42, Num 7, pp 780-793, issn 0018-9340Article
Approach to partially self-checking combinational circuits designDJORDJEVIC, Goran Lj; STOJCEV, Mile K; STANKOVIC, Tatjana R et al.Microelectronics journal. 2004, Vol 35, Num 12, pp 945-952, issn 0959-8324, 8 p.Article
Algorithm level re-computing using implementation diversity: A register transfer level concurrent error detection techniqueKARRI, Ramesh; WU, Kaijie.IEEE transactions on very large scale integration (VLSI) systems. 2002, Vol 10, Num 6, pp 864-875, issn 1063-8210, 12 p.Article
Reflections on the pentium division bugBLUM, M; WASSERMAN, H.IEEE transactions on computers. 1996, Vol 45, Num 4, pp 385-393, issn 0018-9340Article
Design of parallel fault-secure encoders for systematic cyclic block transmission codesJABER, Houssein; MONTEIRO, Fabrice; PIESTRAK, Stanisław J et al.Microelectronics journal. 2009, Vol 40, Num 12, pp 1686-1697, issn 0959-8324, 12 p.Article
An adaptive checker for the fully differential analog codeSTRATIGOPOULOS, Haralampos-G. D; MAKRIS, Yiorgos.IEEE journal of solid-state circuits. 2006, Vol 41, Num 6, pp 1421-1429, issn 0018-9200, 9 p.Article