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Results 1 to 25 of 441

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MODELL DES DEPLETION TRANSISTORS = UN MODELE POUR LE TRANSISTOR A DEPLETIONPOSDZIECH G.1979; NACHR.-TECH., ELEKTRON.; DDR; DA. 1979; VOL. 29; NO 6; PP. 236-239; BIBL. 4 REF.Article

ANALYSIS AND CHARACTERIZATION OF THE DEPLETION-MODE IGFETEL MANSY YA.1980; IEEE J. SOLID-STATE CIRCUITS; ISSN 0018-9200; USA; DA. 1980; VOL. 15; NO 3; PP. 331-340; BIBL. 11 REF.Article

SMALL GEOMETRY DEPLETED BASE BIPOLAR TRANSISTORS (BSIT)-VLSI DEVICES.STORK JMC; PLUMMER JD.1981; IEEE TRANSACTIONS ON ELECTRON DEVICES; ISSN 0018-9383; USA; DA. 1981; VOL. 28; NO 11; PP. 1354-1363; BIBL. 20 REF.Article

ON THE INTERPRETATION OF DLTS SPECTRA OF MIS CAPACITORSTHURZO I; KRESAKOVA K; JAKUBOVIE J et al.1982; J. PHYS. D; ISSN 0022-3727; GBR; DA. 1982; VOL. 15; NO 9; PP. 1751-1764; BIBL. 2 P.Article

TEMPERATURE DEPENDENT THRESHOLD BEHAVIOR OF DEPLETION MODE MOSFETS. CHARACTERIZATION AND SIMULATIONGAENSSLEN FH; JAEGER RC.1979; SOLID STATE ELECTRON.; GBR; DA. 1979; VOL. 22; NO 4; PP. 423-430; BIBL. 9 REF.Article

BEHAVIOR OF ELECTRICALLY SMALL DEPLETION MODE MOSFETS AT LOW TEMPERATUREGAENSSLEN FH; JAEGER RC.1981; SOLID-STATE ELECTRON.; ISSN 0038-1101; GBR; DA. 1981; VOL. 24; NO 3; PP. 215-220; BIBL. 4 REF.Article

COMPUTERGERECHTE MODELLFAMILIE FUER INTEGRIERTE MOS-TRANSISTOREN. II: VERARMUNGSTRANSISTOR, CMOS-TECHNIK = FAMILLE DE MODELES CONVENANT A LA SIMULATION SUR ORDINATEUR DE TRANSISTORS MOS INTEGRES. DEUXIEME PARTIE: TRANSISTOR A APPAUVRISSEMENT EN TECHNOLOGIE MOS COMPLEMENTAIREDIENER KH; FISCHER P; GAERTNER U et al.1980; NACHR.-TECH., ELEKTRON.; DDR; DA. 1980; VOL. 30; NO 4; PP. 155-158; ABS. RUS/ENG/FRE; BIBL. 11 REF.Article

SINGLE-DEVICE-WELL MOSFET'SHAMDY EZ; ELMASRY MI; EL MANSY YA et al.1981; IEEE TRANS. ELECTRON DEVICES; ISSN 0018-9383; USA; DA. 1981; VOL. 28; NO 3; PP. 322-327; BIBL. 11 REF.Article

FABRICATION AND CHARACTERISTICS OF "AUTODOPED DEPLETION VMOSTS"BHATTACHARYYA AB; RATMAN P.1980; SOLID-STATE ELECTRON.; ISSN 0038-1101; GBR; DA. 1980; VOL. 23; NO 10; PP. 1094-1097; BIBL. 4 REF.Article

CAPACITOR COUPLING OF GAAS DEPLETION-MODE F.E.T.S.LIVINGSTONE AW; MELLOR PJT.1980; IEE PROC., PART. 1; ISSN 0143-7100; GBR; DA. 1980; VOL. 127; NO 5; PP. 297-300; BIBL. 4 REF.Article

UNTERSUCHUNGEN AN DOPPEL-SFETS = RECHERCHE SUR LES TRANSISTORS DOUBLES A EFFET DE CHAMP ET A COUCHE D'ARRETKUPFER K.1979; RADIO FERNSEHEN ELEKTRON.; DDR; DA. 1979; VOL. 28; NO 6; PP. 383-384; BIBL. 2 REF.Article

SIMULATION OF IMPURITY FREEZEOUT THROUGH NUMERICAL SOLUTION OF POISSON'S EQUATION WITH APPLICATION TO MOS DEVICE BEHAVIORJAEGER RC; GAENSSLEN FH.1980; IEEE TRANS. ELECTRON DEVICES; ISSN 0018-9383; USA; DA. 1980; VOL. 27; NO 5; PP. 914-920; BIBL. 14 REF.Article

DEPLETION-TYPE M.O.S.F.E.T.S. FOR LOW-TEMPERATURE OPERATIONKAWASHIMA M; KANAMORI M; MATSUMURA M et al.1979; ELECTRON. LETTERS; GBR; DA. 1979; VOL. 15; NO 23; PP. 759-760; BIBL. 3 REF.Article

IN0.53 GA0.47 AS FET'S WITH INSULATOR-ASSISTED SCHOTTKY GATESO'CONNOR P; PEARSALL TP; CHENG KY et al.1982; ELECTRON DEVICE LETTERS; ISSN 0193-8576; USA; DA. 1982; VOL. 3; NO 3; PP. 64-66; BIBL. 16 REF.Article

MANUFACTURING TOLERANCE OF CAPACITOR COUPLED GAAS FET LOGIC CIRCUITSLIVINGSTONE AW; WELBOURN AD; BLAU GL et al.1982; ELECTRON DEVICE LETT.; ISSN 0193-8576; USA; DA. 1982; VOL. 3; NO 10; PP. 284-286; BIBL. 2 REF.Article

SIMPLE ANALYTICAL MODELS FOR THE TEMPERATURE DEPENDENT THRESHOLD BEHAVIOR OF DEPLETION-MODE DEVICESJAEGER RC; GAENSSLEN FH.1979; I.E.E.E. J. SOLID-STATE CIRCUITS; USA; DA. 1979; VOL. 14; NO 2; PP. 423-430; BIBL. 19 REF.Article

A SIMPLIFIED SELF-ALIGNED AL-GATE MOS TECHNOLOGY FOR HIGH PERFORMANCE DEPLETION-LOGIC CIRCUITSPEREIRA DE SOUZA J; CHARRY E.1979; I.E.E.E. J. SOLID-STATE CIRCUITS; USA; DA. 1979; VOL. 14; NO 3; PP. 651-653; BIBL. 7 REF.Article

LOW-TEMPERATURE OPERATION OF BIPOLAR AND MOS DEVICESOOSAKA F; NAKAMURA T.1978; FUJITSU SCI. TECH. J.; JPN; DA. 1978; VOL. 14; NO 3; PP. 53-76; BIBL. 15 REF.Article

PROPAGATION DELAY TIME AND DELAY-POWER PRODUCT OF A SMALL-SIZED DSA-ED GATE CIRCUITHAYASHI Y.1978; I.E.E.E. J. SOLID-STATE CIRCUITS; USA; DA. 1978; VOL. 13; NO 5; PP. 726-728; BIBL. 4 REF.Article

GEOMETRIC EFFECTS ON THE GATE-CONTROLLED CAPACITORSLUTSKY EB; ZEMEL JN.1980; IEEE TRANS. ELECTRON DEVICES; ISSN 0018-9383; USA; DA. 1980; VOL. 27; NO 9; PP. 1843-1846; BIBL. 10 REF.Article

SIMPLE ANALYTICAL MODELS FOR THE TEMPERATURE DEPENDENT THRESHOLD BEHAVIOR OF DEPLETION-MODE DEVICESJAEGER RC; GAENSSLEN FH.1979; I.E.E.E. TRANS. ELECTRON DEVICES; USA; DA. 1979; VOL. 26; NO 4; PP. 501-508; BIBL. 19 REF.Article

A THEORETICAL AND EXPERIMENTAL STUDY OF DMOS ENHANCEMENT/DEPLETION LOGIC. = ETUDE THEORIQUE ET EXPERIMENTALE DE LA LOGIQUE MOS A DOUBLE DIFFUSION UTILISANT DES TRANSISTORS A ENRICHISSEMENT ET A DEPLETIONDECLERCQ MJ; LAURENT T.1977; I.E.E.E.J. SOLID-STATE CIRCUITS; U.S.A.; DA. 1977; VOL. 12; NO 3; PP. 264-270; BIBL. 17 REF.Article

DEPLETION-MODE GAAS MOS FET.LILE DL; CLAWSON AR; COLLINS DA et al.1976; APPL. PHYS. LETTERS; U.S.A.; DA. 1976; VOL. 29; NO 3; PP. 207-208; BIBL. 6 REF.Article

DEPLETION-MODE M.O.S.F.E.T. MODEL INCLUDING A FIELD-DEPENDENT SURFACE MOBILITYBACCARANI G.1980; I.E.E. PROC., I; GBR; DA. 1980; VOL. 127; NO 2; PP. 62-66; BIBL. 8 REF.Article

EXTRACTION OF AVERAGE DOPING DENSITY AND JUNCTION DEPTH IN AN ION-IMPLANTED DEEP-DEPLETION TRANSISTORWU DS.1980; IEEE TRANS. ELECTRON DEVICES; ISSN 0018-9383; USA; DA. 1980; VOL. 27; NO 5; PP. 995-997; BIBL. 2 REF.Article

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